US4556984A
Expired / Lapsed
US
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Frequency multiplier/divider apparatus and method
Assignee: General Dynamics Mission Systems Inc
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Filing: 1983-12-27
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Granted: 1985-12-03
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Expires: 2003-12-27
Abstract
Abstract Apparatus and method for generating an output signal as a function of an input, or reference signal. The apparatus consists of a numerically controlled oscillator having an output signal whose output frequency is determined by the input of a pair of frequency select inputs to the NCO. A control unit operates a multiplexer which allows one of the pair of frequency select inputs to be transmitted to the NCO. The increase in the number of variables provides an increase in the number of different step frequencies the FMD may be operated at.
Inventors
- 👤 Thad J. Genrich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:34
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991; H03L7/0994; H03L7/16; H03L7/18; H03L7/1806
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
133 words
Clocked frequency multiplier/divider (FMD) apparatus, having first and second frequency select inputs and a reference frequency input, said apparatus comprising: an adder having a first input, a second input, an output and a carry output; a register having an input, a carry input, a clock input, a carry output and an output, said input being coupled to said output of said adder, said carry input being coupled to said carry output of said adder, said clock input being coupled to said reference input of said FMD and said output being coupled to said second input of said adder; selecting means for selecting one of said first and second frequency select inputs of said FMD; control means for controlling said selecting means; and an output having a predetermined relationship to said reference frequency input.
Claim 2
Dependent Claim
133 words
Clocked frequency multiplier/divider (FMD) apparatus, having first and second frequency select inputs and a reference frequency input, said apparatus comprising: an adder having a first input, a second input, an output and a carry output; a register having an input, a carry input, a clock input, a carry output and an output, said input being coupled to said output of said adder, said carry input being coupled to said carry output of said adder, said clock input being coupled to said reference input of said FMD and said output being coupled to said second input of said adder; selecting means for selecting one of said first and second frequency select inputs of said FMD; control means for controlling said selecting means; and an output having a predetermined relationship to said reference frequency input.
Claim 3
Dependent Claim
64 words
The FMD of claim 1 wherein said selecting means comprises a multiplexer having a first input, a second input, a select input and an output, said first input being coupled to said frequency select input of said FMD, said second input being coupled to said second frequency select input of said FMD, and said output being coupled to said first input of said adder.
Claim 4
Dependent Claim
74 words
The FMD of claim 2 wherein said control means comprises a control unit having a carry input, a clock input, an output and a select output, said carry input being coupled to said carry output of said register, said clock input being coupled to said reference frequency input of said FMD, said output being coupled to said output of said FMD and said select output being coupled to said select input of said multiplexer.
Claim 5
Independent Claim
133 words
A method of providing an output signal from a frequency multiplier/divider (FMD) at a desired frequency comprising the steps of: transmitting one of a first and a second frequency select inputs to an adder; adding said one of said first and said second frequency select inputs to an output word from a register to produce an output word with a carry bit from said adder; loading said output word and said carry bit of said adder to said register on a clock pulse; transmitting said output word of said register to said adder and transmitting a carry bit from said register to a control unit on said clock pulse; selecting one of said first and second frequency select inputs for transmitting to said adder; and producing an output signal on a clock signal.
Claim 6
Independent Claim
133 words
A method of providing an output signal from a frequency multiplier/divider (FMD) at a desired frequency comprising the steps of: transmitting one of a first and a second frequency select inputs to an adder; adding said one of said first and said second frequency select inputs to an output word from a register to produce an output word with a carry bit from said adder; loading said output word and said carry bit of said adder to said register on a clock pulse; transmitting said output word of said register to said adder and transmitting a carry bit from said register to a control unit on said clock pulse; selecting one of said first and second frequency select inputs for transmitting to said adder; and producing an output signal on a clock signal.
Claim 7
Dependent Claim
55 words
The method of claim 4 wherein said providing one of said first and said second frequency select inputs to said adder comprises the steps of: providing first and second frequency select inputs to a multiplexer; and selecting one of said first and said second frequency select inputs to pass through said multiplexer to said adder.
Claim 8
Dependent Claim
56 words
The method of claim 5 wherein said selecting of one of said first and second frequency select inputs for transmitting to said adder comprises the steps of: producing a select signal; and transmitting said select signal to said multiplexer to select said one of said first and said second frequency select inputs, on said clock pulse.
Claim 9
Dependent Claim
228 words
A frequency multiplier/divider (FMD) apparatus, having a first and second frequency select inputs, a reference frequency input and a frequency output, said apparatus comprising: a multiplexer having a first input, a second input, a select input and an output, said first input being coupled to said first frequency select input of said FMD and said second input being coupled to said second frequency select input of said FMD; an adder having a first input, a second input, an output and a carry output, said first input being coupled to said output of said multiplexer; a register having an input, a carry input, a clock input, a carry output and an output, said input being coupled to said output of said adder, said carry input being coupled to said carry output of said adder, said clock input being coupled to said reference frequency input of said FMD and said output being coupled to said second input of said adder; and a control unit having a carry bit input, a clock input, an output and a select output, said carry bit input being coupled to said carry bit output of said register, said clock input being coupled to said reference frequency input of said FMD, said output being coupled to said frequency output of said said FMD and said select output being coupled to said select input of said multiplexer.
Claim 10
Dependent Claim
228 words
A frequency multiplier/divider (FMD) apparatus, having a first and second frequency select inputs, a reference frequency input and a frequency output, said apparatus comprising: a multiplexer having a first input, a second input, a select input and an output, said first input being coupled to said first frequency select input of said FMD and said second input being coupled to said second frequency select input of said FMD; an adder having a first input, a second input, an output and a carry output, said first input being coupled to said output of said multiplexer; a register having an input, a carry input, a clock input, a carry output and an output, said input being coupled to said output of said adder, said carry input being coupled to said carry output of said adder, said clock input being coupled to said reference frequency input of said FMD and said output being coupled to said second input of said adder; and a control unit having a carry bit input, a clock input, an output and a select output, said carry bit input being coupled to said carry bit output of said register, said clock input being coupled to said reference frequency input of said FMD, said output being coupled to said frequency output of said said FMD and said select output being coupled to said select input of said multiplexer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-02 | 1989-06-03 | 1989-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-02 | 1993-06-03 | 1993-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-02 | 1997-06-03 | 1997-12-03 | $7700.00 | Window Closed / Lapsed |