Semiconductor storage device

Claim 2

A semiconductor storage device comprising: a plurality of common data lines for delivering information data from plural memory cells selected out of a plurality of memory cells; a plurality of amplifier circuits being provided which correspond in number to the number of said plurality of common data lines and which provide output signals in accordance with data received from said common data lines, respectively; a plurality of first testing logical circuits for providing output signals in response to the outputs of said amplifier circuits of which each one of at least one of said first testing logical circuits is coupled to plural amplifier circuits, said plural amplifier circuits being a numerical subset of said plurality of amplifier circuits; and a second testing logical circuit being coupled to said plurality of testing logical circuits and providing a corresponding test data output in accordance with the output signals received from each one of said plurality of first testing logical circuits, wherein each one of said plurality of first testing logical circuits includes input and output signal lines for inputting thereto signals outputted by said amplifier circuits and outputting therefrom corresponding output signals, and wherein the required number of output signal lines is less than the number of input signal lines for each one of said plurality of first testing logical circuits.

Claim 3

A semiconductor storage device according to claim 1, wherein each of said plurality of amplifier circuits is a main amplifier for amplifying the memory cell information delivered to the corresponding common data line.

Claim 4

A semiconductor storage device according to claim 2, wherein each of said plurality of first testing logical circuits is respectively supplied with the output signals from respective subsets of plural amplifier circuits, each subset defining two or more amplifier circuits.

Claim 5

A semiconductor storage device according to claim 3, wherein each of said plurality of common data lines is formed of a pair of data lines, whereby the memory cell information is transmitted as complementary signals.

Claim 6

A semiconductor storage device according to claim 4, wherein each one of said plurality of amplifier circuits is provided with a pair of data lines, whereby each output signal of each amplifier circuit is transmitted as complementary signals via said pair of data lines.

Claim 7

A semiconductor storage device according to claim 5, wherein each one of said plurality of first testing logical circuits includes means which detects either an equality or inequality between sets of output information data supplied thereto from said plural amplifier circuits associated therewith.

Claim 8

A semiconductor storage device according to claim 6, wherein said second testing logical circuit includes second means which detects whether or not there is equality between the sets of information from the plural memory cells selected from said plurality of memory cells based on the output signals from each one of said first testing logical circuits.

Claim 9

A semiconductor storage device according to claim 7, wherein each one of said first testing logical circuits is disposed in close proximity with the respective plural amplifier circuits associated therewith with respect to a layout arrangement of the same on a substrate.

Claim 10

A semiconductor storage device according to claim 8, wherein each said plural amplifier circuits comprises a pair of main amplifiers wherein the corresponding first testing logical circuit associated therewith is centrally disposed on said substrate between them such that the total length of the input signal lines of each one of said first testing logical circuits, which are connected to the output data lines of a corresponding pair of main amplifiers, is minimized, and wherein said second testing logical circuit is centrally disposed in the layout arrangement of said plurality of first testing logical circuit and said second testing logical circuit on said substrate so as to minimize the required total length of the wiring lines of a corresponding wiring layer connecting the output signal lines of said plurality of first testing logical circuits to the inputs of said second testing logical circuit in the layout arrangement.

Claim 11

A semiconductor storage device according to claim 9, wherein each one of said plurality of first testing logical circuits comprises a first AND logical circuit having a pair of inputs responsive to non-inverted data line signals of a corresponding pair of main amplifiers associated therewith, and a second AND logical circuit having a pair of inputs responsive to logically inverted data line signals of a corresponding pair of main amplifiers associated therewith.

Claim 12

A semiconductor storage device according to claim 10, wherein said second testing logical circuit comprises a pair of AND logical circuits which are respectively responsive to the AND logical circuits associated with the non-inverted data line signals and to the AND logical circuits associated with the logically inverted data line signals of said first testing logical circuits in response to a multi-bit testing mode timing signal which is indicative of a testing mode operation.

Claim 13

A semiconductor storage device according to claim 11, wherein each of the AND logical circuits of said plurality of first testing logical circuits and of said second testing logical circuit are comprised of a series connection of a NAND gate and an inverter logical gate.

Claim 14

A semiconductor storage device according to claim 12, wherein said second testing logical circuit further includes a NOR logical gate having a pair of inputs respectively coupled to respective outputs of the pair of NAND gates thereat and having an output selectively coupled to both an output of one of said pair of AND logical circuits through a pair of series-connected inverter logical gates and to an output of the other of said pair of AND logical circuits through a further inverter logical gate.

Claim 15

A semiconductor storage device according to claim 13, wherein the outputs of said pair of AND logical circuits are respectively selectively coupled to complementary common input/output lines of said semiconductor storage device via respective inverter logical buffer circuits during said testing mode operation and in turn to an output terminal of said semiconductor storage device via an input/output circuit thereof.

Claim 16

A semiconductor storage device according to claim 14, wherein said memory cells are of the dynamic RAM type.

Claim 17

A semiconductor storage device according to claim 14, wherein said memory cells are of the SRAM type.

Claim 18

A semiconductor storage device according to claim 14, wherein each one of said plurality of common data lines is associated with a separate array of memory cells of a matrix arrangement of rows and columns of memory cells, and wherein the number of such separate array of cells corresponds to the number of main amplifiers.

Claim 19

A semiconductor storage device according to claim 17, wherein respective pairs of separate arrays of memory cells are associated with and have disposed therebetween, in said layout arrangement on said substrate, a respective sensing amplifier arrangement which provides outputs of selected memory cells in the form of complementary binary signals to corresponding complementary data lines and which outputs are inputted to a corresponding pair of main amplifiers associated therewith.

Claim 20

A semiconductor storage device according to claim 18, wherein said memory cells are of the dynamic RAM type.

Claim 21

A semiconductor storage device comprising: a plurality of common data lines for delivering information data from plural memory cells selected out of a plurality of memory cells; a plurality of amplifier circuits being provided which correspond in number to the number of said plurality of common data lines and which provide output signals in accordance with data received from said common data lines, respectively; a plurality of first testing logical circuits for providing output signals in response to the outputs of said amplifier circuits of which each one of at least one of said first testing logical circuits is coupled to plural amplifier circuits, said plural amplifier circuits being a numerical subset of said plurality of amplifier circuits; and a second testing logical circuit being coupled to said plurality of testing logical circuits and providing a corresponding test data output in accordance with the output signals received from each one of said plurality of first testing logical circuits, means for selectively delivering one output signal from the output signals of said plurality of amplifier circuits and the output signal of said second testing logical circuit to an output terminal, wherein each one of said plurality of first testing logical circuits includes input and output signal lines for inputting thereto signals outputted by said amplifier circuits and outputting therefrom corresponding output signals, and wherein the required number of output signal lines is less than the number of input signal lines for each one of said plurality of first testing logical circuits.

Claim 22

A semiconductor storage device comprising: a plurality of common data lines for delivering information data from plural memory cells selected out of a plurality of memory cells; a plurality of amplifier circuits being provided which correspond in number to the number of said plurality of common data lines and which provide output signals in accordance with data received from said common data lines, respectively; a plurality of first testing logical circuits for providing output signals in response to the outputs of said amplifier circuits of which each one of at least one of said first testing logical circuits is coupled to plural amplifier circuits, said plural amplifier circuits being a numerical subset of said plurality of amplifier circuits; and a second testing logical circuit being coupled to said plurality of testing logical circuits and providing a corresponding test data output in accordance with the output signals received from each one of said plurality of first testing logical circuits, means for selectively delivering one output signal from the output signals of said plurality of amplifier circuits and the output signal of said second testing logical circuit to an output terminal, wherein each one of said plurality of first testing logical circuits includes input and output signal lines for inputting thereto signals outputted by said amplifier circuits and outputting therefrom corresponding output signals, and wherein the required number of output signal lines is less than the number of input signal lines for each one of said plurality of first testing logical circuits.

Claim 23

A semiconductor storage device according to claim 20, wherein each of said plurality of first testing logical circuits is respectively supplied with the output signals from respective subsets of plural amplifier circuits, each subset defining two or more amplifier circuits.

Claim 24

A semiconductor storage device according to claim 21, wherein each of said plurality of common data lines is formed of a pair of data lines, whereby the memory cell information is transmitted as complementary signals.

Claim 25

A semiconductor storage device according to claim 22, wherein each one of said plurality of amplifier circuits is provided with a pair of data lines, whereby each output signal of each amplifier circuit is transmitted as complementary signals, via said pair of data lines.

Claim 26

A semiconductor storage device according to claim 23, wherein each one of said plurality of first testing logical circuits includes means which detects either an equality or inequality between sets of output information data supplied thereto from said plural amplifier circuits associated therewith.

Claim 27

A semiconductor storage device according to claim 24, wherein said second testing logical circuit includes second means which detects whether or not there is equality between the sets of information from the plural memory cells selected from said plurality of memory cells based on the output signals from each one of said first testing logical circuits.

Claim 28

A semiconductor storage device according to claim 20, wherein each one of said first testing logical circuits is disposed in close proximity with the respective plural amplifier circuits associated therewith with respect to a layout arrangement of the same on a substrate.

Claim 29

A semiconductor storage device according to claim 26, wherein each said plural amplifier circuits comprises a pair of main amplifiers wherein the corresponding first testing logical circuit associated therewith is centrally disposed on said substrate between them such that the total length of the input signal lines of each one of said first testing logical circuits, which are connected to the output data lines of a corresponding pair of main amplifiers, is minimized, and wherein said second testing logical circuit is centrally disposed in the layout arrangement of said plurality of first testing logical circuit and said second testing logical circuit on said substrate so as to minimize the required total length of the wiring lines of a corresponding wiring layer connecting the output signal lines of said plurality of first testing logical circuits to the inputs of said second testing logical circuit in the layout arrangement.

Claim 30

A semiconductor storage device according to claim 27, wherein each one of said plurality of first testing logical circuits comprises a first AND logical circuit having a pair of inputs responsive to non-inverted data line signals of a corresponding pair of main amplifiers associated therewith, and a second AND logical circuit having a pair of inputs responsive to logically inverted data line signals of a corresponding pair of main amplifiers associated therewith.

Claim 31

A semiconductor storage device according to claim 28, wherein said second testing logical circuit comprises a pair of AND logical circuits which are respectively responsive to the AND logical circuits associated with the non-inverted data line signals and to the AND logical circuits associated with the logically inverted data line signals of said first testing logical circuits in response to a multi-bit testing mode timing signal which is indicative of a testing mode operation.

Claim 32

A semiconductor storage device according to claim 29, wherein each of the AND logical circuits of said plurality of first testing logical circuits and of said second testing logical circuit are comprised of a series connection of a NAND gate and an inverter logical gate.

Claim 33

A semiconductor storage device according to claim 30, wherein said second testing logical circuit further includes a NOR logical gate having a pair of inputs respectively coupled to respective outputs of the pair of NAND gates thereat and having an output selectively coupled to both an output of one of said pair of AND logical circuits through a pair of series-connected inverter logical gates and to an output of the other of said pair of AND logical circuits through a further inverter logical gate.

Claim 34

A semiconductor storage device according to claim 35, wherein the outputs of said pair of AND logical circuits are respectively selectively coupled to complementary common input/output lines of said semiconductor storage device via respective inverter logical buffer circuits during said testing mode operation and in turn to an output terminal of said semiconductor storage device via an input/output circuit thereof.

Claim 35

A semiconductor storage device according to claim 32, wherein said memory cells are of the dynamic RAM type.

Claim 36

A semiconductor storage device according to claim 32, wherein said memory cells are of the SRAM type.

Claim 37

A semiconductor storage device according to claim 34, wherein each one of said plurality of common data lines is associated with a separate array of memory cells of a matrix arrangement of rows and columns of memory cells, and wherein the number of such separate array of cells corresponds to the number of main amplifiers.

Claim 38

A semiconductor storage device according to claim 35, wherein respective pairs of separate arrays of memory cells are associated with and have disposed therebetween, in said layout arrangement on said substrate, a respective sensing amplifier arrangement which provides outputs of selected memory cells in the form of complementary binary signals to corresponding complementary data lines.

Claim 39

A semiconductor storage device according to claim 36, wherein said memory cells are of the dynamic RAM type.