US4313199A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Recirculating loop memory array fault locator
Assignee: International Business Machines Corp
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Filing: 1980-06-26
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Granted: 1982-01-26
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Expires: 2000-06-26
Abstract
Abstract Apparatus is disclosed for quickly testing memory arrays of multiple recirculating loop memory elements and for locating faulty elements, if any, within designated subdivisions of said array. All loops are loaded with identical test bits. The loaded data is verified and faulty elements, if any, are located by means of a plurality of comparison AND gates. Each gate is connected to the output of a respective subdivision of the array elements and produces a first output signal when all such outputs are identical (on a serial bit-by-bit basis) and produces a second output signal when all said outputs are not identical. The output signals from the respective comparison AND gates are sensed in serial succession to locate the array subdivision containing any faulty elements.
Inventors
- 👤 Frederick J. Aichelmann, Jr.
- 👤 Bruce E. Bachman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:19
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/003
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
117 words
Logic means on an array chip for testing the constituent recirculating loop memory elements of said array, said means comprising means for addressing all of said elements and for loading said elements with the same test bits a plurality of comparison gate means, each said comparison gate means being connected to the outputs of a respective subdivision of said array of elements for ANDing said outputs to produce a respective first output signal when all said outputs are identical on a serial bit-by-bit basis and to produce a respective second output signal when all said outputs are not identical, and means for sensing in serial succession the respective output signals from said plurality of comparison gate means.
Claim 2
Dependent Claim
117 words
Logic means on an array chip for testing the constituent recirculating loop memory elements of said array, said means comprising means for addressing all of said elements and for loading said elements with the same test bits a plurality of comparison gate means, each said comparison gate means being connected to the outputs of a respective subdivision of said array of elements for ANDing said outputs to produce a respective first output signal when all said outputs are identical on a serial bit-by-bit basis and to produce a respective second output signal when all said outputs are not identical, and means for sensing in serial succession the respective output signals from said plurality of comparison gate means.
Claim 3
Dependent Claim
39 words
The apparatus defined in claim 1 wherein said means for sensing the respective output signals from said plurality of comparison gate means operates at a serial succession rate commensurate with the rate of recirculation of said loop memory elements.
Claim 4
Dependent Claim
42 words
The apparatus defined in claim 1 wherein said means for sensing the respective output signals from said plurality of comparison gate means operates at a serial succession rate which is substantially faster than the rate of recirculation of said loop memory elements.
Claim 5
Dependent Claim
13 words
The apparatus defined in claim 1 wherein said elements are charge coupled devices.
Claim 6
Dependent Claim
51 words
The apparatus defined in claim 1 or claim 3 wherein said means for sensing the respective output signals from said plurality of comparison gate means comprises an equal plurality of error latches connected to receive respective ones of said output signals, and means for sensing said error latches in serial succession.
Claim 7
Dependent Claim
22 words
The apparatus defined in claim 1 and further including means for ANDing the output signals from all of said comparison gate means.
Claim 8
Dependent Claim
30 words
The apparatus in claim 1 wherein said means for addressing and for loading simultaneously addresses all of said elements and loads said elements in parallel with the same test bits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-01-25 | 1985-07-27 | 1986-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-01-25 | 1989-07-27 | 1990-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-01-25 | 1993-07-27 | 1994-01-26 | $7700.00 | Window Closed / Lapsed |