Adjustable current source and digital/analog converter with autocalibration using such a source

Claim 2

An adjustable current source comprising a bipolar transistor, the base of which receives a signal adapted to approximately set the current which flows therethrough, further comprising a MOS transistor, in series with said bipolar transistor, the gate of which receives an adjustment signal stored by a capacitor connected between its gate and its drain, wherein said bipolar transistor is a NPN transistor and said MOS transistor is an enhanced P-channel transistor, the source of the MOS transistor being connected with a high voltage, its drain being connected with the collector of the bipolar transistor and the emitter of the bipolar transistor being connected with a low voltage source.

Claim 3

An adjustable current source according to claim 1, wherein said adjustment signal originates from a current amplifier supplying an error signal resulting from the comparison between said current source and a reference current source.

Claim 4

A digital/analog converter comprising stages each having a current source, said stages corresponding to lower rank bits and higher rank bits, wherein each of said stages corresponding to higher rank bits includes, an adjustable current source comprising a bipolar transistor, the base of which receives a signal adapted to approximately set the current which flows therethrough, further comprising a MOS transistor, in series with said bipolar transistor, the gate of which receives an adjustment signal stored by a capacitor connected between its gate and its drain, wherein said bipolar transistor is a NPN transistor and said MOS transistor is an enhanced P-channel transistor, the source of the MOS transistor being connected with a high voltage, its drain being connected with the collector of the bipolar transistor and the emitter of the bipolar transistor being connected with a low voltage source.

Claim 5

A digital/analog converter comprising stages each having a current source, said stages corresponding to lower rank bits and higher rank bits, wherein each of said stages corresponding to higher rank bits includes, an adjustable current source comprising a bipolar transistor, the base of which receives a signal adapted to approximately set the current which flows therethrough, further comprising a MOS transistor, in series with said bipolar transistor, the gate of which receives an adjustment signal stored by a capacitor connected between its gate and its drain, wherein said bipolar transistor is a NPN transistor and said MOS transistor is an enhanced P-channel transistor, the source of the MOS transistor being connected with a high voltage, its drain being connected with the collector of the bipolar transistor and the emitter of the bipolar transistor being connected with a low voltage source.

Claim 6

A digital/analog converter according to claim 3, comprising switching and amplifying means for periodically comparing the current in each of the current sources corresponding to the higher rank bits with the sum of the currents of the lower rank bits current sources and for accordingly adjusting the current in said current sources corresponding to the higher rank bits.