US4730123A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for driving a capacitive load which provides low current consumption
Assignee: US Philips Corp
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Filing: 1986-10-29
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Granted: 1988-03-08
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Expires: 2006-10-29
Abstract
Abstract A circuit arrangement for driving a capcitive load comprises a control circuit (1), whose output is the collector of an output transistor (2). The collector is coupled through the gatesource path of a junction field effect transistor (5) and a resistor (6) connected parallel thereto to the capacitive load (8). The drain connection of the J-FET is connected to the supply voltage (Ub). The circuit permits rapid switching of the load while maintaining the current consumption relatively low.
Inventors
- 👤 Fritz A. Wegener
- 👤 Manfred Albach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:15
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/04; H03K17/041; H03K17/0416; H03K17/04166; H03K17/51; H03K17/56; H03K17/567; H03K17/687; H03K17/6877
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
139 words
A circuit arrangement for operation of a capacitive load comprising: a control circuit including an output transistor having a collector connected to an output of the control circuit, a terminal for a source of supply voltage for the circuit arrangement, a junction field effect transistor having a drain, source and a gate, means coupling said output of the control circuit to said capacitive load via the gate-source path of said field effect transistor, a resistor connected in parallel with said gate-source path of the field effect transistor, means connecting the drain of the field effect transistor to said supply voltage terminal, and wherein the collector-emitter path of the output transistor is in parallel with the load so that the capacitive load will be discharged via said resistor and said output transistor when the output transistor is made to conduct.
Claim 2
Dependent Claim
139 words
A circuit arrangement for operation of a capacitive load comprising: a control circuit including an output transistor having a collector connected to an output of the control circuit, a terminal for a source of supply voltage for the circuit arrangement, a junction field effect transistor having a drain, source and a gate, means coupling said output of the control circuit to said capacitive load via the gate-source path of said field effect transistor, a resistor connected in parallel with said gate-source path of the field effect transistor, means connecting the drain of the field effect transistor to said supply voltage terminal, and wherein the collector-emitter path of the output transistor is in parallel with the load so that the capacitive load will be discharged via said resistor and said output transistor when the output transistor is made to conduct.
Claim 3
Dependent Claim
15 words
A circuit arrangement as claimed in claim 1, characterized in that the resistor is adjustable.
Claim 4
Dependent Claim
27 words
A circuit arrangement as claimed in claim 1, wherein the output transistor is an NPN bipolar transistor with its emitter connected to a point of reference potential.
Claim 5
Dependent Claim
56 words
A circuit arrangement as claimed in claim 1, wherein the control circuit comprises a comparator having first and second inputs whereby the output transistor is switched between a cut-off state and a conductive state, and vice versa, in accordance with results of a comparison of signals applied to said first and second inputs of the comparator.
Claim 6
Dependent Claim
37 words
A circuit arrangement as claimed in claim 1, wherein the output transistor comprises a bipolar transistor having a base electrode supplied with a switching signal that switches said output transistor between conduction and cut-off, and vice versa.
Claim 7
Dependent Claim
55 words
A circuit arrangement as claimed in claim 1, wherein the output transistor is an NPN bipolar transistor with its emitter connected to a point of reference potential, and said capacitive load has one terminal connected to the source electrode of said field effect transistor and a second terminal connected to said point of reference potential.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-08 | 1991-09-07 | 1992-03-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-08 | 1995-09-07 | 1996-03-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-08 | 1999-09-07 | 2000-03-08 | $7700.00 | Window Closed / Lapsed |