US4912730A
Expired / Lapsed
US
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High speed reception of encoded data utilizing dual phase resynchronizing clock recovery
Assignee: Harris Corp
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Filing: 1988-10-03
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Granted: 1990-03-27
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Expires: 2008-10-03
Abstract
Abstract A mechanism for recovering respective binary states of an input data signal in synchronism with transitions of the input data signal carries out the following sequence of steps. First, the binary state of the input data signal is sampled in accordance with consecutively occurring transitions of a high speed clock signal, the repetition frequency of which is at least three times the data transition rate. Upon the occurrence of a difference in binary state of successive samples of the input data signal at consecutive transitions of the clock signal, a signal representative of such a change is generated. In response to this change of state or transition-representative signal, the binary state of a delayed version of the input data signal, at a time whereat the input data signal is stable, is sampled. In order to reliably monitor the state of the communication link over which the data is transmitted, the binary state of the input data signal is periodically sampled. In addition, to prevent anomalies or `glitches` in the input data signal from erroneously being detected as data transitions, once the binary state of the input data signal is sampled, any further sampling is prevented for a prescribed period of time subsequent to that sampling, thereby permitting the data to stabilize.
Inventors
- 👤 Richard A. Erhart
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:23
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
239 words
An apparatus for recovering respective binary states of an input data signal in synchronism with transitions of said input data signal, and generating an output signal representative thereof comprising: first means, coupled to receive said input data and a digital clock signal, for sampling the binary state of said input data signal in accordance with successive positive-going transitions in said digital clock signal; second means, coupled to receive said input data and said digital clock signal, for sampling the binary state of said input data signal in accordance with successive negative-going transitions in said digital clock signal; third means, coupled to said first and second means, for generating a first signal representative of a change in said input data signal from one binary state to another in accordance with a prescribed relationship between respective samples of the binary state of said input data signal as sampled by said first and second means at consecutively occurring transitions of said digital clock signal; and fourth means, coupled to one of said first and second means, and to said third means, for sampling a delayed version of a sampled binary state of said input data signal as sampled by said one of said first and second means, at a time that is displaced with respect a change in the binary state of said input data signals as represented by the generation of said first signal, and producing an output signal representative thereof.
Claim 2
Independent Claim
239 words
An apparatus for recovering respective binary states of an input data signal in synchronism with transitions of said input data signal, and generating an output signal representative thereof comprising: first means, coupled to receive said input data and a digital clock signal, for sampling the binary state of said input data signal in accordance with successive positive-going transitions in said digital clock signal; second means, coupled to receive said input data and said digital clock signal, for sampling the binary state of said input data signal in accordance with successive negative-going transitions in said digital clock signal; third means, coupled to said first and second means, for generating a first signal representative of a change in said input data signal from one binary state to another in accordance with a prescribed relationship between respective samples of the binary state of said input data signal as sampled by said first and second means at consecutively occurring transitions of said digital clock signal; and fourth means, coupled to one of said first and second means, and to said third means, for sampling a delayed version of a sampled binary state of said input data signal as sampled by said one of said first and second means, at a time that is displaced with respect a change in the binary state of said input data signals as represented by the generation of said first signal, and producing an output signal representative thereof.
Claim 3
Dependent Claim
30 words
An apparatus according to claim 1, wherein said digital clock signal has a repetition rate that is at least three times the encoded data rate of said input data signal.
Claim 4
Dependent Claim
52 words
An apparat us according to claim 1, wherein said third means includes means for generating said first signal in response to a difference between respective samples of the binary state of said input data signal as sampled by said first and second means at consecutively occurring transitions of said digital clock signal.
Claim 5
Dependent Claim
60 words
An apparatus according to claim 1, wherein said fourth means includes clock divider means, coupled to receive said digital clock signal and said first signal, for generating a sampling control clock, through which said delayed version of a sampled binary state of said input data signal is sampled, at a frequency lower than the frequency of said digital clock signals.
Claim 6
Dependent Claim
24 words
An apparatus according to claim 4, wherein said fourth means includes means for resetting said clock divider means in response to said first signal.
Claim 7
Independent Claim
191 words
A method for recovering respective binary states of an input data signal in synchronism with transitions of said input data signal, and generating an output signal representative thereof comprising the steps of: (a) sampling the binary state of said input data signal in accordance with successive positive-going transitions in a digital clock signal; (b) sampling the binary state of said input data signal in accordance with successive negative-going transitions in said digital clock signal; (c) generating a first signal representative of a change in said input data signal from one binary state to another in accordance with a prescribed relationship between respective samples of the binary state of said input data signal as sampled in steps (a) and (b) at consecutively occurring transitions of said digital clock signal; and (d) sampling a delayed version of a sampled binary state of said input data signal, as sampled in one of steps (a) and (b), at a time that is displaced with respect a change in the binary state of said input data signals as represented by the generation of said first signal in step (c), and producing an output signal representative thereof.
Claim 8
Independent Claim
191 words
A method for recovering respective binary states of an input data signal in synchronism with transitions of said input data signal, and generating an output signal representative thereof comprising the steps of: (a) sampling the binary state of said input data signal in accordance with successive positive-going transitions in a digital clock signal; (b) sampling the binary state of said input data signal in accordance with successive negative-going transitions in said digital clock signal; (c) generating a first signal representative of a change in said input data signal from one binary state to another in accordance with a prescribed relationship between respective samples of the binary state of said input data signal as sampled in steps (a) and (b) at consecutively occurring transitions of said digital clock signal; and (d) sampling a delayed version of a sampled binary state of said input data signal, as sampled in one of steps (a) and (b), at a time that is displaced with respect a change in the binary state of said input data signals as represented by the generation of said first signal in step (c), and producing an output signal representative thereof.
Claim 9
Dependent Claim
30 words
A method according to claim 6, wherein said digital clock signal has a repetition rate that is at least three times the encoded data rate of said input data signal.
Claim 10
Dependent Claim
47 words
A method according to claim 6, wherein step (c) includes generating said first signal in response to a difference between respective samples of the binary state of said input data signal as sampled in steps (a) and (b) at consecutively occurring transitions of said digital clock signal.
Claim 11
Dependent Claim
47 words
A method according to claim 6, wherein step (d) includes the step of generating a sampling control clock, through which said delayed version of a sampled binary state of said input data signal is sampled, at a frequency lower than the frequency of said digital clock signals.
Claim 12
Dependent Claim
20 words
A method according to claim 9, wherein step (d) resetting said sampling control clock in response to said first signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-26 | 1993-09-25 | 1994-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-26 | 1997-09-25 | 1998-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-26 | 2001-09-25 | 2002-03-27 | $7700.00 | Window Closed / Lapsed |