Patent US4912708A successfully refreshed from Google Patents.
US4912708A
Expired / Lapsed
US
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Automatic microprocessor fault recovery system
Assignee: Siemens Transmission Systems Inc
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Filing: 1988-03-22
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Granted: 1990-03-27
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Expires: 2008-03-22
Abstract
Abstract Telecommunications equipment used in outdoor environments are subjected to harsh electrical conditions. Circuits which utilize sequential components, such as microprocessors, can therefore become confused due to extraneous power surges which may occur in the harsh conditions existing around the equipment. Furthermore, maintenance of the equipment has become much more automated, often leaving the equipment unattended for extended periods of time. In accordance with the invention, a circuit which automatically and reliably recognizes the failure conditions in the microprocessor, and automatically forces the microprocessor to recover is described.
Inventors
- 👤 Rolf H. G. Wendt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:29
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/0763
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
123 words
An automatic fault recovery circuit for a microprocessor based system, comprising byte-wide binary counter means for generating a pseudorandom bit pattern; watchdog timer means having a reset input for resetting said watchdog timer to prevent said watchdog timer means from timing out; means for using said pseudorandom bit pattern to reset said watchdog timer means, such that said watchdog timer means can only be reset by said pseudorandom bit pattern; counter means associated with said watchdog timer means which is incremented after each reset, such that a subsequent reset input must correspond to the current counter pattern to prevent said watchdog timer means from timing out; and means for providing an interrupt signal to said microprocessor when said watchdog timer means times out.
Claim 2
Dependent Claim
123 words
An automatic fault recovery circuit for a microprocessor based system, comprising byte-wide binary counter means for generating a pseudorandom bit pattern; watchdog timer means having a reset input for resetting said watchdog timer to prevent said watchdog timer means from timing out; means for using said pseudorandom bit pattern to reset said watchdog timer means, such that said watchdog timer means can only be reset by said pseudorandom bit pattern; counter means associated with said watchdog timer means which is incremented after each reset, such that a subsequent reset input must correspond to the current counter pattern to prevent said watchdog timer means from timing out; and means for providing an interrupt signal to said microprocessor when said watchdog timer means times out.
Claim 3
Dependent Claim
21 words
An automatic fault recovery circuit in accordance with claim 1 wherein said interrupt signal produces a non-maskable interrupt of said microprocessor.
Claim 4
Dependent Claim
21 words
An automatic fault recovery circuit in accordance with claim 1 wherein said binary counter is at least an 8-bit binary counter.
Claim 5
Dependent Claim
54 words
An automatic fault recovery circuit in accordance with claim 1 further comprising: comparator means for comparing a data byte stored in said binary counter to a data byte on a data line from said microprocessor, and for generating an output signal for resetting said watchdog timer when the two data bytes compared are equal.
Claim 6
Dependent Claim
28 words
An automatic fault recovery circuit in accordance with claim 4 wherein said counter is reset either when said watchdog timer times out or when a system reset occurs.
Claim 7
Dependent Claim
20 words
An automatic fault recovery circuit in accordance with claim 4 wherein the pseudorandom bit pattern is a sequential data byte.
Claim 8
Dependent Claim
26 words
An automatic fault recovery circuit in accordance with claim 1 wherein said watchdog timer means is a counter which times out by reaching a predetermined value.
Claim 9
Dependent Claim
31 words
An automatic fault recovery circuit in accordance with claim 6, further including means for distributing said sequential data byte at a plurality of address locations in software associated with said microprocessor.
References Cited (Backward Citations)
US4118792A
Cited
US4405982A
Cited
US4538273A
Cited
US4566101A
Cited
US4529842A
Cited
US4594685A
Cited
US4683568A
Cited
US4649537A
Cited
WO1986003312A1
Cited
US4709376A
Cited
US4727549A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-26 | 1993-09-25 | 1994-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-26 | 1997-09-25 | 1998-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-26 | 2001-09-25 | 2002-03-27 | $7700.00 | Window Closed / Lapsed |