Patent US4912666A successfully refreshed from Google Patents.
US4912666A
Expired / Lapsed
US
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Pseudo-random noise code generating circuit
Assignee: Faurecia Clarion Electronics Co Ltd
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Filing: 1987-09-16
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Granted: 1990-03-27
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Expires: 2007-09-16
Abstract
Abstract A pseudo-random noise code generating circuit having a shift register constructed by a plurality of unit circuits, each of which consists of an AND gate, an exclusive logical sum gate, a steering gate, which sets initial values and changes over the shift register operation, and a flipflop constituting the shift register.
Inventors
- 👤 Masaaki Harada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:44
CPC Classifications
G; G11; G11C; G11C19/00; H; H03; H03K; H03K3/00; H03K3/84
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
322 words
A pseudo-random noise code generating circuit comprising a shift register which includes a plurality of units, each having: (a) an exclusive logical sum gate having first and second inputs and having an output, (b) an AND gate having first and second inputs and having an output connected to said second input of said exclusive logical sum gate, (c) a steering gate having first and second inputs, an output, and a control input, said steering gate coupling one of its first and second inputs selected by its control input to its output, said first input of said steering gate being coupled to said output of said exclusive logical sum gate, and (d) a flipflop having a data input connected to said output of said steering gate, having a clock input, and having an output; said circuit including a first cascade input terminal coupled to said second input of each said AND gate; said circuit including a second cascade input terminal coupled to the first input of the exclusive logical sum gate of a first of said units; said circuit including a cascade output terminal and means for coupling the output of a selected one of said flipflops to said cascade output terminal, the flipflop of each said unit other than a second of said units having its output coupled to the first input of the exclusive logical sum gate of a respective one of said units other than said first of said units; said circuit including means for supplying a respective signal having a selected logical condition to said first input of each said AND gate; said circuit including means for supplying a clock signal to said clock input of each said flipflop; said circuit including means for supplying to said second input of each of said steering gates a respective initial value signal; and said circuit including means for supplying a control signal to siad control input of each said steering gate.
Claim 2
Dependent Claim
322 words
A pseudo-random noise code generating circuit comprising a shift register which includes a plurality of units, each having: (a) an exclusive logical sum gate having first and second inputs and having an output, (b) an AND gate having first and second inputs and having an output connected to said second input of said exclusive logical sum gate, (c) a steering gate having first and second inputs, an output, and a control input, said steering gate coupling one of its first and second inputs selected by its control input to its output, said first input of said steering gate being coupled to said output of said exclusive logical sum gate, and (d) a flipflop having a data input connected to said output of said steering gate, having a clock input, and having an output; said circuit including a first cascade input terminal coupled to said second input of each said AND gate; said circuit including a second cascade input terminal coupled to the first input of the exclusive logical sum gate of a first of said units; said circuit including a cascade output terminal and means for coupling the output of a selected one of said flipflops to said cascade output terminal, the flipflop of each said unit other than a second of said units having its output coupled to the first input of the exclusive logical sum gate of a respective one of said units other than said first of said units; said circuit including means for supplying a respective signal having a selected logical condition to said first input of each said AND gate; said circuit including means for supplying a clock signal to said clock input of each said flipflop; said circuit including means for supplying to said second input of each of said steering gates a respective initial value signal; and said circuit including means for supplying a control signal to siad control input of each said steering gate.
Claim 3
Dependent Claim
98 words
A circuit of claim 1, wherein said means for coupling the output of said selected one of said flipflops to said cascade output terminal includes a multiplexer having a plurality of data inputs which are each coupled to the output of a respective one of said flipflops, having a data output which is coupled to said cascade output terminal, and having select inputs which select one of said data inputs thereof to be coupled by said multiplexer to its data output; and includes means for supplying a select signal to each of said select inputs of said multiplexer.
Claim 4
Dependent Claim
26 words
A circuit of claim 2, including a further cascade output terminal which is coupled to the output of said flipflop of said second of said units.
Claim 5
Dependent Claim
200 words
A pseudo-random generator circuit comprising: first and second cascade input terminals; a cascade output terminal; a first flipflop and a plurality of second flipflops, said first and second flipflops each having a data input, a data output and a clock input; means for supplying a clock signal to saidclock input of each of said first and second flipflops; means for applying to said cascade output terminal a signal present at the data output of said first flipflop; a first exclusive logic sum gate and a plurality of second exclusive logic sum gates, said first and second exclusive logic sum gates each having first and second inputs and having an output coupled to the data input of a respective one of said first and second flipflops, said first exclusive logic sum gate having its first input coupled to said second cascade input terminal, and the data output of each of said second flipflops being coupled to the first input of a respective one of said second exclusive logic sum gates, and gating means coupled to said first cascade input terminal for applying to said second input of each of said first and second exclusive logic sum gates a respective logic signal.
Claim 6
Dependent Claim
200 words
A pseudo-random generator circuit comprising: first and second cascade input terminals; a cascade output terminal; a first flipflop and a plurality of second flipflops, said first and second flipflops each having a data input, a data output and a clock input; means for supplying a clock signal to saidclock input of each of said first and second flipflops; means for applying to said cascade output terminal a signal present at the data output of said first flipflop; a first exclusive logic sum gate and a plurality of second exclusive logic sum gates, said first and second exclusive logic sum gates each having first and second inputs and having an output coupled to the data input of a respective one of said first and second flipflops, said first exclusive logic sum gate having its first input coupled to said second cascade input terminal, and the data output of each of said second flipflops being coupled to the first input of a respective one of said second exclusive logic sum gates, and gating means coupled to said first cascade input terminal for applying to said second input of each of said first and second exclusive logic sum gates a respective logic signal.
Claim 7
Dependent Claim
88 words
A circuit of claim 4, including a further cascade output terminal; and incuding a multiplexer having a plurality of data inputs which are each coupled to the output of a respective one of said flipflops, having a data output which is couplted to said further cascade output terminal, and having select inputs which select one of the data inputs thereof to be coupled by said multiplexer to its data output, and including means for supplying a respective select signal to each of said select inputs of said multiplexer.
Claim 8
Dependent Claim
82 words
A circuit of claim 5, wherein said gating means includes a plurality of AND gates each having first and second inputs and having an output coupled to the second input of a respective one of said exclusive logic sum gates, said second input of each of said AND gates being coupled to said first cascade input terminal, and said circuit including means for applying to said first input of each of said AND gates a respective signal having a selected logical condition.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-26 | 1993-09-25 | 1994-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-26 | 1997-09-25 | 1998-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-26 | 2001-09-25 | 2002-03-27 | $7700.00 | Window Closed / Lapsed |