Device for generating binary digit pseudo-random sequences

Claim 1

A device for generating pseudorandom sequences of binary digits, of the type comprising seven like logic sequential blocks synchronously driven by a predetermined frequency signal and each thereof assuming at the output the logic level of the related input depending on each pulse of said signal and assuming at said output a predetermined logic level as a predetermined logic level is present at an input thereof as supplied through a RESET line, the outputs of the first, second, third, fourth, fifth, sixth blocks being respectively coupled to the inputs of the second, third, fourth, fifth, sixth, seventh blocks and the outputs of said sixth and seventh blocks being coupled to corresponding inputs of an Exclusive-OR logic circuit the output thereof is coupled to the input of the first block; said device being associated with a logic apparatus coupling four discrete lines thereon a binary code information is transmitted having a frequency equal to the frequency of said signal with a line for transmitting binary code signals having a frequency which is four times said one frequency; said logic apparatus being of the type comprising: four two-input AND logic circuits, the first inputs thereof are correspondingly coupled to said four lines and the second inputs thereof are derived from a line effective to supply the synchronization signal; four Exclusive-OR logic circuits, provided with at least two inputs, and respectively a first, second, third and fourth Exclusive-OR circuits, the first inputs thereof being correspondingly coupled to the outputs of said AND circuits and the second inputs thereof being coupled to said device; a multiplexer provided with four inputs thereto there are correspondingly coupled the outputs of said first, second, third and fourth Exclusive-OR circuits and the output thereof is coupled to said transmission line; said device being characterized in that it comprises: a fifth Exclusive-OR logic circuit (20), provided with three inputs coupled to the outputs Q1,Q4,Q6 respectively of said first, fourth and sixth sequential blocks A1,A4,A6 and the output thereof is coupled to the second input of said first Exclusive-OR circuit (21) the input thereof is coupled to the output Q6 of said sixth sequential logic block A6 and the output thereof is coupled to the second input of said second Exclusive-OR circuit (17); a seventh Exclusive-OR logic circuit (22) provided with three inputs respectively coupled to the outputs Q2,Q4,Q5 of said second, fourth and fifth sequential blocks A2,A4,A5 and the output thereof is coupled to the second input of said third Exclusive-OR logic circuit (18); an eighth Exclusive-OR logic circuit (23) provided with two inputs coupled to the outputs Q2,Q5 respectively of said second and fifth sequential blocks A2,A5 and the output thereof is coupled to the second input of said fourth Esclusive-OR circuit (19); said device being further characterized in that said RESET line (30) is coupled to a third input of said fourth Exclusive-OR circuit (19) and being furthermore coupled to the SET inputs of said first, third, fourth, sixth and seventh sequential blocks A1,A3,A4,A6,A7 as well as to the RESET inputs of the remaining said sequential blocks A2,A5.

Claim 2

A device for generating pseudorandom sequences of binary digits, of the type comprising seven like logic sequential blocks synchronously driven by a predetermined frequency signal and each thereof assuming at the output the logic level of the related input depending on each pulse of said signal and assuming at said output a predetermined logic level as a predetermined logic level is present at an input thereof as supplied through a RESET line, the outputs of the first, second, third, fourth, fifth, sixth blocks being respectively coupled to the inputs of the second, third, fourth, fifth, sixth, seventh blocks and the outputs of said sixth and seventh blocks being coupled to corresponding inputs of an Exclusive-OR logic circuit the output thereof is coupled to the input of the first block; said device being associated with a logic apparatus coupling four discrete lines thereon a binary code information is transmitted having a frequency equal to the frequency of said signal with a line for transmitting binary code signals having a frequency which is four times said one frequency; said logic apparatus being of the type comprising: four two-input AND logic circuits, the first inputs thereof are correspondingly coupled to said four lines and the second inputs thereof are derived from a line effective to supply the synchronization signal; four Exclusive-OR logic circuits, provided with at least two inputs, and respectively a first, second, third and fourth Exclusive-OR circuits, the first inputs thereof being correspondingly coupled to the outputs of said AND circuits and the second inputs thereof being coupled to said device; a multiplexer provided with four inputs thereto there are correspondingly coupled the outputs of said first, second, third and fourth Exclusive-OR circuits and the output thereof is coupled to said transmission line; said device being characterized in that it comprises: a fifth Exclusive-OR logic circuit (20), provided with three inputs coupled to the outputs Q1,Q4,Q6 respectively of said first, fourth and sixth sequential blocks A1,A4,A6 and the output thereof is coupled to the second input of said first Exclusive-OR circuit (21) the input thereof is coupled to the output Q6 of said sixth sequential logic block A6 and the output thereof is coupled to the second input of said second Exclusive-OR circuit (17); a seventh Exclusive-OR logic circuit (22) provided with three inputs respectively coupled to the outputs Q2,Q4,Q5 of said second, fourth and fifth sequential blocks A2,A4,A5 and the output thereof is coupled to the second input of said third Exclusive-OR logic circuit (18); an eighth Exclusive-OR logic circuit (23) provided with two inputs coupled to the outputs Q2,Q5 respectively of said second and fifth sequential blocks A2,A5 and the output thereof is coupled to the second input of said fourth Esclusive-OR circuit (19); said device being further characterized in that said RESET line (30) is coupled to a third input of said fourth Exclusive-OR circuit (19) and being furthermore coupled to the SET inputs of said first, third, fourth, sixth and seventh sequential blocks A1,A3,A4,A6,A7 as well as to the RESET inputs of the remaining said sequential blocks A2,A5.