US4023026A
Expired / Lapsed
US
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Pseudo-random coder with improved near range rejection
Assignee: International Telephone and Telegraph Corp
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Filing: 1975-12-15
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Granted: 1977-05-10
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Expires: 1995-12-15
Abstract
Abstract A modified maximal length PRC (pseudo-random code) sequence generator for use in autocorrelating systems such as CW, bi-phase modulated PRC radar systems. The code generator for the system is a modified version of a known shift register and feedback arrangement, which provides a wordlength of 2n - 1 as known in the prior art. Means are shown for adding a zero in the sequence of n-1 zeroes which always occur within the PRC word according to pseudo-noise theory. The result is an autocorrelation function having no residual value for several bits on either side of the correlation peak, thereby providing a theoretically infinite range discrimination in the near vicinity of a true range value.
Inventors
- 👤 Francis J. O'Farrell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 03:56
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/84; G; G06; G06F; G06F7/00; G06F7/58; G06F7/582; G06F7/584; G06F2207/00; G06F2207/58; G06F2207/581; G06F2207/583
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
153 words
A system for generating a maximum length pseudo-random code, including digital word means for generating a repetitive serial digital word of L bits as a psdueo-random sequence, where L = 2 n and n = the number of stages in said digital word means, each of said stages being capable of assuming a first or second binary condition, the combination comprising: first means connected to respond to said binary condition of a predetermined number of said stages to produce an identifying signal for the instantaneous code condition corresponding to the presence of the (n-1)th successive contiguous digit having a value corresponding to said first binary condition; and second means responsive to said identifying signal from said first means, for generating the next code digit having a value corresponding to said first binary condition, said system being connected to thereafter continue to generate the digits of said code through the 2 n th digit.
Claim 2
Independent Claim
153 words
A system for generating a maximum length pseudo-random code, including digital word means for generating a repetitive serial digital word of L bits as a psdueo-random sequence, where L = 2 n and n = the number of stages in said digital word means, each of said stages being capable of assuming a first or second binary condition, the combination comprising: first means connected to respond to said binary condition of a predetermined number of said stages to produce an identifying signal for the instantaneous code condition corresponding to the presence of the (n-1)th successive contiguous digit having a value corresponding to said first binary condition; and second means responsive to said identifying signal from said first means, for generating the next code digit having a value corresponding to said first binary condition, said system being connected to thereafter continue to generate the digits of said code through the 2 n th digit.
Claim 3
Dependent Claim
21 words
Apparatus according to claim 1, in which said first and second binary conditions are defined as logical ones and zeroes, respectively.
Claim 4
Dependent Claim
40 words
Apparatus according to claim 1 in which said digital word means is a digital shift register responsive to a clock pulse signal and means for providing feedback in a manner such that said repetitive serial digital word is pseudo-random sequence.
Claim 5
Dependent Claim
173 words
A pseudo-random coded digital sequence generator having a code output terminal and comprising: a plurality of n stages comprising a digital shift register, each of said register stages being a bi-stable device having Q and Q outputs, stages being responsive to a clock pulse, the Q output of each stage being connected to control the binary condition of a next successive stage concurrent with a clock pulse; a first logic circuit arrangement responsive to a predetermined arrangement of said bi-stable stage Q outputs to provide a control signal at a time when said Q outputs assume a predetermined pattern corresponding to occurrence of a string of n-1 consecutive zeroes in said pseudo-random sequence; and a second logic circuit arrangement responsive to said control signal and the Q output of a predetermined one of said register stages to control the next successive register stage to modify the signal thereby controlling the binary condition of said next successive register stage to produce an additional zero in said pseudo-random sequence within said string of consecutive zeroes.
Claim 6
Dependent Claim
173 words
A pseudo-random coded digital sequence generator having a code output terminal and comprising: a plurality of n stages comprising a digital shift register, each of said register stages being a bi-stable device having Q and Q outputs, stages being responsive to a clock pulse, the Q output of each stage being connected to control the binary condition of a next successive stage concurrent with a clock pulse; a first logic circuit arrangement responsive to a predetermined arrangement of said bi-stable stage Q outputs to provide a control signal at a time when said Q outputs assume a predetermined pattern corresponding to occurrence of a string of n-1 consecutive zeroes in said pseudo-random sequence; and a second logic circuit arrangement responsive to said control signal and the Q output of a predetermined one of said register stages to control the next successive register stage to modify the signal thereby controlling the binary condition of said next successive register stage to produce an additional zero in said pseudo-random sequence within said string of consecutive zeroes.
Claim 7
Dependent Claim
14 words
Apparatus according to claim 4 in which said bi-stable register stages are flip-flop circuits.
Claim 8
Dependent Claim
50 words
Apparatus according to claim 4 in which said second logic circuit arrangement is further defined as containing circuits operating to add said additional zero after the occurrence of said string of n-1 zeroes in response to said control signal generated concurrently with the n-1 the zero in said pseudo-random sequence.
Claim 9
Dependent Claim
103 words
Apparatus according to claim 6 in which said second logic circuit arrangement comprises first and second exclusive OR circuits, each having two inputs and an output, the inputs of said first exclusive OR circuit being connected one to said code output terminal and the other to said predetermined register stage Q output, said second exclusive OR circuit having its input connected, one to the output of said first exclusive OR circuit and the other to the output of said first means, said second exclusive OR circuit output being connected to provide the connection to said succeeding register stage following said predetermined register stage.
Claim 10
Dependent Claim
29 words
Apparatus according to claim 6 in which said first logic circuit arrangement comprises at least one logical AND circuit providing n-1 inputs and an output providing said control signal.
Claim 11
Dependent Claim
103 words
Apparatus according to claim 8 in which said second logic circuit arrangement comprises first and second exclusive OR circuits, each having two inputs and an output, the inputs of said first exclusive OR circuit being connected one to said code output terminal and the other to said predetermined register stage Q output, said second exclusive OR circuit having its input connected, one to the output of said first exclusive OR circuit and the other to the output of said first means, said second OR exclusive circuit output being connected to provide the connection to said succeeding register stage following said predetermined register stage.
Claim 12
Dependent Claim
14 words
Apparatus according to claim 9 in which said bi-stable register stages are flip-flop circuits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-05-09 | 1980-11-08 | 1981-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-05-09 | 1984-11-08 | 1985-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-05-09 | 1988-11-08 | 1989-05-10 | $7700.00 | Window Closed / Lapsed |