Current source as a microwave biasing element

Claim 2

An amplifier biasing circuit comprising: (a) a first stage field effect transistor amplifier having gate, source and drain electrodes; (b) a second stage field effect transistor amplifier having gate, source and drain electrodes; (c) means for providing a constant current between the second stage source electrode and the first stage drain electrode; (d) means for blocking the flow of direct current voltage from the first to the second stage.

Claim 3

A biasing circuit according to claim 1, wherein the constant current means comprises a third field effect transistor having gate, source and drain electrodes, and a resistor connected between the drain and gate electrodes of the third field effect transistor and further wherein the third field effect transistor source and gate electrodes are commonly connected to the first stage drain electrode and the third field effect transistor drain electrode is connected to the second stage source electrode.

Claim 4

A biasing circuit according to claim 2, wherein the third field effect transistor is a gallium-arsenide field effect transistor.

Claim 5

A biasing circuit according to claim 1, further comprising: (a) means for providing a shunt feedback signal from the first stage drain electrode output to the first stage gate electrode input; (b) means for providing a shunt feedback signal from the second stage drain electrode output to the second stage gate electrode input.

Claim 6

A biasing circuit according to claim 1, wherein the first and second stage amplifiers are both gallium-arsenide field effect transistors.

Claim 7

A biasing circuit according to claim 1, wherein the first stage field effect transistor has a gate length of 250 microns and the second stage field effect transistor has a gate length of 350 microns.

Claim 8

An amplifier circuit comprising: (a) a first stage field effect transistor amplifier having gate, source and drain electrodes, further comprising: (i) an input terminal connected to the gate electrode of the first stage field effect transistor; (ii) means for providing a shunt feedback signal from the drain electrode of the first stage field effect transistor to the gate electrode of the first stage field effect transistor, and including first means for blocking direct current signals at radio frequencies; (iii) means for biasing the source electrode of the first stage field effect transistor, whereby the direct current voltage present at the source electrode of the first stage field effect transistor is "floated" and independent from alternating current ground; (b) a second stage field effect transistor amplifier having gate, source and drain electrodes, further comprising: (i) means for applying direct current power to the drain electrode of the second stage field effect transistor; (ii) means for providing a shunt feedback signal from the drain electrode of the second stage field effect transistor to the gate electrode of the second stage field effect transistor and including second means for blocking direct current; (iii) means for biasing the source electrode of the second stage field effect transistor, whereby the direct current voltage present at the source electrode of the second stage field effect transistor is "floated" and independent from alternating current ground; (iv) a resistive divider network connected between the drain electrode of the second stage field effect transistor and ground for supplying bias voltage to the gate electrode of the second stage field effect transistor; (c) means for providing a constant current between the second stage source electrode and the first stage drain electrode, the constant current means including a third field effect transistor having gate, source and drain electrodes, wherein the third field effect transistor source and gate electrodes are commonly connected to the first stage drain electrode, the third field effect transistor drain electrode is connected to the second stage source electrode, and a resistor is connected between the drain and gate electrodes of the third field effect transistor; and (d) third means for blocking the flow of direct current voltage from the first to the second stage.

Claim 9

An amplifier circuit comprising: (a) a first stage field effect transistor amplifier having gate, source and drain electrodes, further comprising: (i) an input terminal connected to the gate electrode of the first stage field effect transistor; (ii) means for providing a shunt feedback signal from the drain electrode of the first stage field effect transistor to the gate electrode of the first stage field effect transistor, and including first means for blocking direct current signals at radio frequencies; (iii) means for biasing the source electrode of the first stage field effect transistor, whereby the direct current voltage present at the source electrode of the first stage field effect transistor is "floated" and independent from alternating current ground; (b) a second stage field effect transistor amplifier having gate, source and drain electrodes, further comprising: (i) means for applying direct current power to the drain electrode of the second stage field effect transistor; (ii) means for providing a shunt feedback signal from the drain electrode of the second stage field effect transistor to the gate electrode of the second stage field effect transistor and including second means for blocking direct current; (iii) means for biasing the source electrode of the second stage field effect transistor, whereby the direct current voltage present at the source electrode of the second stage field effect transistor is "floated" and independent from alternating current ground; (iv) a resistive divider network connected between the drain electrode of the second stage field effect transistor and ground for supplying bias voltage to the gate electrode of the second stage field effect transistor; (c) means for providing a constant current between the second stage source electrode and the first stage drain electrode, the constant current means including a third field effect transistor having gate, source and drain electrodes, wherein the third field effect transistor source and gate electrodes are commonly connected to the first stage drain electrode, the third field effect transistor drain electrode is connected to the second stage source electrode, and a resistor is connected between the drain and gate electrodes of the third field effect transistor; and (d) third means for blocking the flow of direct current voltage from the first to the second stage.

Claim 10

A biasing circuit according to claim 7, wherein the first and second stage amplifiers are both gallium-arsenide field effect transistors.

Claim 11

A biasing circuit according to claim 7, wherein the third field effect transistor is a gallium-arsenide field effect transistor.

Claim 12

A biasing circuit according to claim 7, wherein the first stage field effect transistor has a gate length of 250 microns and the second stage field effect transistor has a gate length of 350 microns.