Bus master having selective burst initiation

Claim 1

A bus master for use with a memory system capable of transferring operands to said bus master in bursts in response to a burst request signal provided by the bus master, the bus master comprising: a cache for storing in each of a first plurality of cache lines, a second plurality of said operands, an address tag for each cache line, and a third plurality of valid bits, each of the valid bits indicating validity of a respective one of said operands in a respective cache line when set, the second plurality equaling the third plurality; cache control means coupled to the cache for accessing said cache to determine if a selected operand in the second plurality of the operands having a selected access address is stored in said cache, the cache control means providing a tag hit signal if the address tag of one of said cache lines is identical to a tag portion of said selected access address, and a valid entry signal if at least one of said third plurality of valid bits in said one cache line is set; and burst control means coupled to the cache control means for providing said burst request signal to the memory unless the cache control means provides either the tag hit signal or the valid entry signal, thereby preventing replacement by burst filling of said one cache line.