US4908693A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wiring structure of semiconductor pressure sensor
Assignee: Sumitomo Electric Industries Ltd
•
Filing: 1987-12-08
•
Granted: 1990-03-13
•
Expires: 2007-12-08
Abstract
Abstract A semiconductor pressure sensor comprises a sensor chip including an etching stop layer of high concentration impurity ions formed by ion implantation of impurity ions into a substrate of silicon single crystal or by deposition and diffusion and an epitaxial growth layer of silicon single crystal on the etching stop layer, a recess formed in the back of the sensor chip by etching, circuit elements formed on the sensor chip, diffusion leads for connecting the circuit elements, connecting regions, each formed between the etching stop layer and a predetermined position on the surface of the sensor chip, and diffusion regions, each formed between the predetermined position and one of terminals of the circuit elements.
Inventors
- 👤 Masanori Nishiguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:07
CPC Classifications
G; G01; G01L; G01L9/00; G01L9/0041; G01L9/0051; G01L9/0052; G01L9/0054; G01L9/0042
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
119 words
A semiconductor pressure sensor, comprising: a sensor chip including an etching stop layer of high concentration impurity ions formed by ion implantation of impurity ions into a substrate of silicon single crystal or by deposition and diffusion, and an epitaxial growth layer of silicon single crystal on said etching stop layer; a recess formed in the back of said sensor chip through etching; circuit elements formed on said sensor chip; diffusion lead portions for wiring said circuit elements; first connecting regions, each formed between said etching stop layer and a first predetermined position on the surface of said sensor chip; and first diffusion regions, each formed between said first predetermined position and one of terminals of said circuit elements.
Claim 2
Dependent Claim
119 words
A semiconductor pressure sensor, comprising: a sensor chip including an etching stop layer of high concentration impurity ions formed by ion implantation of impurity ions into a substrate of silicon single crystal or by deposition and diffusion, and an epitaxial growth layer of silicon single crystal on said etching stop layer; a recess formed in the back of said sensor chip through etching; circuit elements formed on said sensor chip; diffusion lead portions for wiring said circuit elements; first connecting regions, each formed between said etching stop layer and a first predetermined position on the surface of said sensor chip; and first diffusion regions, each formed between said first predetermined position and one of terminals of said circuit elements.
Claim 3
Dependent Claim
20 words
A semiconductor pressure sensor as claimed in claim 1, wherein said first connecting regions are formed by impurity ion implantation.
Claim 4
Dependent Claim
48 words
A semiconductor pressure sensor as claimed in claim 1, wherein said first connecting regions are formed by providing holes extended to at least the adjoining portion of said etching stop layer at said first predetermined positions and by forming conductive diffusion regions in the surroundings of said holes.
Claim 5
Dependent Claim
63 words
A semiconductive pressure sensor as claimed in claim 1, further comprising wiring layers formed in parallel to said etching stop layer; second connecting regions, each formed between one of said wiring regions and a second predetermined position on the surface of said sensor chip; and second diffusion regions, each formed between said second predetermined position and one of terminals of said circuit elements.
Claim 6
Dependent Claim
20 words
A semiconductor pressure sensor as claimed in claim 4, wherein said second connecting regions are formed by impurity ion implantation.
Claim 7
Dependent Claim
47 words
A semiconductor pressure sensor as claimed in claim 4, wherein said second connecting regions are formed by providing holes extended to at least the adjoining portion of said wiring region at said second predetermined position and by forming conductive diffusion regions in the surroundings of said holes.
References Cited (Backward Citations)
US3994009A
Cited
US4203128A
Cited
EP0010204A1
Cited
US4314226A
Cited
US4320664A
Cited
US4332000A
Cited
US4410871A
Cited
US4426768A
Cited
US4588472A
Cited
EP0150827A2
Cited
US4654621A
Cited
US4672354A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-12 | 1993-09-11 | 1994-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-12 | 1997-09-11 | 1998-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-12 | 2001-09-11 | 2002-03-13 | $7700.00 | Window Closed / Lapsed |