Method for enciphering and deciphering instructions in a microcomputer, and a microcomputer used for effecting same

Claim 2

A deciphering apparatus for a microcomputer, comprising: instruction receiving means for receiving at least two types of instruction codes, each type of instruction code being enciphered in accordance with a corresponding predetermined enciphering format, all instructions being enciphered and at least two types of instruction codes are enciphered in accordance with different enciphering formats; address signal generating means for generating addresses of said at least two type of instruction codes; discriminating means, operatively connected to said address-signal generating means, for discriminating the type of instruction code received by said instruction receiving means, in dependence on a value of a least significant bit in the addresses, to read said instruction code; at least two instruction decipherers, each decipherer deciphering said instruction codes in accordance with a corresponding predetermined deciphering format, each decipherer having a different deciphering format producing different deciphered results for the same instruction codes and said at least two decipherers deciphering the corresponding type instructions in a one to one correspondence; and selecting means, operatively connected to said discriminating means and between said instruction receiving means and said at least two instruction decipherers, for selectively supplying an instruction code to only one of said at least two instruction decipherers in response to discrimination by said discriminating means.

Claim 3

A deciphering apparatus for a microcomputer, comprising: instruction receiving means for receiving at least two types of instruction codes, each type of instruction code being enciphered in accordance with a corresponding predetermined enciphering format, all instructions being enciphered and at least two types of instructions are enciphered in accordance with different enciphering formats; address signal generating means for generating addresses of said at least two types of instruction codes; discriminating means, operatively connected to said address signal generating means, for dicriminating the type of instruction code received by said instruction receiving means, in dependence on a value of a least significant bit in the addresses, to read said instruction code; at least two instruction decipheres operatively connected to said instruction receiving means, each decipherer deciphering said instruction codes in accordance with a corresponding predetermined deciphering format, each decipherer having a different deciphering format producing different deciphering results for the same instruction codes and said at least two decipherers deciphering the corresponding type instructions in a one to one correspondence; and selecting means, operatively connected to said discriminating means and said at least two instruction decipherers, for selectively outputting the deciphered results from one of said at least two instruction decipherers in dependence upon the discrimination by said discrimination means.

Claim 4

A deciphering apparatus for a microcomputer, comprising: instruction receiving means for receiving at least two types of instruction codes, each type of instruction code being enciphered in accordance with a corresponding predetermined enciphering format, all instructions being enciphered and at least two types of instructions are enciphered in accordance with different enciphering formats; address signal generating means for generating addresses of said at least two types of instruction codes; discriminating means, operatively connected to said address signal generating means, for dicriminating the type of instruction code received by said instruction receiving means, in dependence on a value of a least significant bit in the addresses, to read said instruction code; at least two instruction decipheres operatively connected to said instruction receiving means, each decipherer deciphering said instruction codes in accordance with a corresponding predetermined deciphering format, each decipherer having a different deciphering format producing different deciphering results for the same instruction codes and said at least two decipherers deciphering the corresponding type instructions in a one to one correspondence; and selecting means, operatively connected to said discriminating means and said at least two instruction decipherers, for selectively outputting the deciphered results from one of said at least two instruction decipherers in dependence upon the discrimination by said discrimination means.

Claim 5

A deciphering apparatus for a microcomputer capable of executing a plurality of types of instructions, the microcomputer including: a read only memory for storing a program having instructions of an instruction set, the program being constructed from a combination of first type instruction codes enciphered by a first enciphering format and second type instruction codes enciphered by a second enciphering format; a data bus connected to said read only memory; an address bus connected to said read only memory; a program counter, connected to said address bus, for generating an address to access said read only memory; and a control unit for generating control signals to control the microcomputer and external circuits; and said apparatus comprising: a first instruction decipherer, connected to said control unit, for supplying a deciphered instruction code, and capable of deciphering all of the first type instruction codes corresponding to said plurality of types of instructions, in a one to one correspondence; a second instruction decipherer, connected to said control unit, for supplying the deciphered instruction codes, and capable of deciphering all of the first type instruction codes corresponding to said plurality of types of instructions, in a one to one correspondence; a selecting circuit, connected between said data bus and said first and second instruction decipherers, for selectively supplying the output of said read only memory to one of said first and second instruction decipherers; and a discriminating circuit, connected between said address bus and said selecting circuit, for controlling said selecting circuit in response to a least significant bit of the address to supply the first or the second type instruction code read from said read only memory to a corresponding one of said first and second instruction decipherers and whereby the program constructed from the combination of said first type instruction codes and said second type instruction codes is executed.

Claim 6

A deciphering apparatus for a microcomputer capable of executing a plurality of types of instructions, the microcomputer including: a read only memory for storing a program having instructions of an instruction set, the program being constructed from a combination of first type instruction codes enciphered by a first enciphering format and second type instruction codes enciphered by a second enciphering format; a data bus connected to said read only memory; an address bus connected to said read only memory; a program counter, connected to said address bus, for generating an address to access said read only memory; and a control unit for generating control signals to control the microcomputer and external circuits; and said apparatus comprising: a first instruction decipherer, connected to said control unit, for supplying a deciphered instruction code, and capable of deciphering all of the first type instruction codes corresponding to said plurality of types of instructions, in a one to one correspondence; a second instruction decipherer, connected to said control unit, for supplying the deciphered instruction codes, and capable of deciphering all of the first type instruction codes corresponding to said plurality of types of instructions, in a one to one correspondence; a selecting circuit, connected between said data bus and said first and second instruction decipherers, for selectively supplying the output of said read only memory to one of said first and second instruction decipherers; and a discriminating circuit, connected between said address bus and said selecting circuit, for controlling said selecting circuit in response to a least significant bit of the address to supply the first or the second type instruction code read from said read only memory to a corresponding one of said first and second instruction decipherers and whereby the program constructed from the combination of said first type instruction codes and said second type instruction codes is executed.

Claim 7

A deciphering apparatus for microcomputer capable of executing a plurality of types of instructions, said microcomputer including: a read only memory for storing a program having instructions of an instruction set, the program being contructed from a combination of first type instruction codes enciphered by a first enciphering format and second type instruction codes enciphered by a second enciphering format; a data bus connected to said read only memory; an address bus connected to said read only memory; a program counter, connected to said address bus, for generating an address to access said read only memory; and a control unit for generating control signals to control the microcomputer itself and external circuits; and said apparatus comprising: a first instruction decipherer, connected to said control unit, for supplying a deciphered instruction code, capable of deciphering all of the first type instruction codes corresponding to said plurality of types of instructions in a one to one correspondence; a second instruction decipherer, connected to said control unit, for supplying the deciphered instructions, capable of deciphering all of the second type instruction codes corresponding to said plurality of types of instructions in a one to one correspondence; a selecting circuit, connected between outputs of said first and second instruction decipherers and said control unit, for selectively outputting the deciphered results from one of said first and second instruction decipherers; and a discriminating circuit, connected between said address bus and said selecting circuit, for controlling said selecting circuit in response to a least significant bit of the address to supply the first or the second type instruction code read from said read only memory to a corresponding one of said first and second instruction decipherers; and whereby the program constructed from the combination of said first type instruction codes and said second type instruction codes is executed.

Claim 8

A deciphering apparatus for microcomputer capable of executing a plurality of types of instructions, said microcomputer including: a read only memory for storing a program having instructions of an instruction set, the program being contructed from a combination of first type instruction codes enciphered by a first enciphering format and second type instruction codes enciphered by a second enciphering format; a data bus connected to said read only memory; an address bus connected to said read only memory; a program counter, connected to said address bus, for generating an address to access said read only memory; and a control unit for generating control signals to control the microcomputer itself and external circuits; and said apparatus comprising: a first instruction decipherer, connected to said control unit, for supplying a deciphered instruction code, capable of deciphering all of the first type instruction codes corresponding to said plurality of types of instructions in a one to one correspondence; a second instruction decipherer, connected to said control unit, for supplying the deciphered instructions, capable of deciphering all of the second type instruction codes corresponding to said plurality of types of instructions in a one to one correspondence; a selecting circuit, connected between outputs of said first and second instruction decipherers and said control unit, for selectively outputting the deciphered results from one of said first and second instruction decipherers; and a discriminating circuit, connected between said address bus and said selecting circuit, for controlling said selecting circuit in response to a least significant bit of the address to supply the first or the second type instruction code read from said read only memory to a corresponding one of said first and second instruction decipherers; and whereby the program constructed from the combination of said first type instruction codes and said second type instruction codes is executed.

Claim 9

A deciphering apparatus for a microcomputer, comprising: instruction receiving means for receiving at least two types of instruction codes, each type of instruction code being enciphered in accordance with a corresponding predetermined enciphering format, all instructions being enciphered and at least two types of instruction codes are enciphered in accordance with different enciphering formats; address signal generating means for generating addresses of said at least two type of instruction codes; discriminating means, operatively connected to said address-signal generating means, for discriminating the type of instruction code received by said instruction receiving means, in dependence on a value of a predetermined bit in the addresses, selected from among a least significant bit through a most significant bit, to read said instruction code; at least two instruction decipherers, each decipherer deciphering said instruction codes in accordance with a corresponding predetermined deciphering format, each decipherer having a different deciphering format producing different deciphered results for the same instruction codes and said at least two decipherers deciphering the corresponding type instructions in a one to one correspondence; and selecting means, operatively connected to said discriminating means and between said instruction receiving means and said at least two instruction decipherers, for selectively supplying an instruction code to only one of said at least two instruction decipherers in response to discrimination by said discriminating means.

Claim 10

A deciphering apparatus for a microcomputer, comprising: instruction receiving means for receiving at least two types of instruction codes, each type of instruction code being enciphered in accordance with a corresponding predetermined enciphering format, all instructions being enciphered and at least two types of instruction codes are enciphered in accordance with different enciphering formats; address signal generating means for generating addresses of said at least two type of instruction codes; discriminating means, operatively connected to said address-signal generating means, for discriminating the type of instruction code received by said instruction receiving means, in dependence on a value of a predetermined bit in the addresses, selected from among a least significant bit through a most significant bit, to read said instruction code; at least two instruction decipherers, each decipherer deciphering said instruction codes in accordance with a corresponding predetermined deciphering format, each decipherer having a different deciphering format producing different deciphered results for the same instruction codes and said at least two decipherers deciphering the corresponding type instructions in a one to one correspondence; and selecting means, operatively connected to said discriminating means and between said instruction receiving means and said at least two instruction decipherers, for selectively supplying an instruction code to only one of said at least two instruction decipherers in response to discrimination by said discriminating means.

Claim 11

An apparatus as set forth in claim 5, wherein said discriminating means comprises means for generating a selecting signal from the predetermined bit of each one of the addresses, and said selecting means comprises gate means, operatively connected to said means for generating the selecting signal and said at least two instruction decipherers, for transferring an instruction code to one of said at least two instruction decipherers, said selecting signal being supplied to said gate means to open or close said gate means.

Claim 12

An apparatus as recited in claim 5, wherein the microcomputer includes an instruction set and each decipherer, when provided with the enciphered instruction set, produces each one of the instructions of the instruction set.

Claim 13

An apparatus as set forth in claim 5, wherein the deciphered results from said at least two instruction decipherers coincide with instructions to be performed by said microcomputer.

Claim 14

An apparatus as set forth in claim 6, wherein said means for generating the selecting signal comprises a signal line, operatively connected between said address signal generating means and siad gate means, transferring the least significant bit of each address.

Claim 15

An apparatus as set forth in claim 6, wherein said means for generating the selecting signal comprises a decoding circuit, operatively connected between said address signal generating means and said gate means, for decoding the least significant bit of each address signal and providing selection signals controlling said gate means.

Claim 16

A deciphering apparatus for a microcomputer, comprising: instruction receiving means for receiving at least two types of instruction codes, each type of instruction code being enciphered in accordance with a corresponding predetermined enciphering format, all instructions being enciphered and at least two types of instructions are encoded in accordance with different enciphering formats; address signal generating means for generating addresses of said at least two types of instruction codes; discriminating means, operatively connected to said address signal generating means, for discriminating the type of instruction code received by said instruction receiving means, in dependence on a value of a predetermined bit in the addresses, selected from among a least significant bit through a most significant bit, to read said instruction code; at least two instruction decipherers operatively connected to said instruction receiving means, each decipherer deciphering said instruction codes in accordance with a corresponding predetermined deciphering format, each decipherer having a different deciphering format producing different deciphering results for the same instruction codes and said at least two decipherers deciphering the corresponding type instructions in a one to one correspondence; and selecting means, operatively connected to said discriminating means and said at least two instruction decipherers, for selectively outputting the deciphered results from one of said at least two instruction decipherers in dependence upon the discrimination by said discrimination means.

Claim 17

A deciphering apparatus for a microcomputer, comprising: instruction receiving means for receiving at least two types of instruction codes, each type of instruction code being enciphered in accordance with a corresponding predetermined enciphering format, all instructions being enciphered and at least two types of instructions are encoded in accordance with different enciphering formats; address signal generating means for generating addresses of said at least two types of instruction codes; discriminating means, operatively connected to said address signal generating means, for discriminating the type of instruction code received by said instruction receiving means, in dependence on a value of a predetermined bit in the addresses, selected from among a least significant bit through a most significant bit, to read said instruction code; at least two instruction decipherers operatively connected to said instruction receiving means, each decipherer deciphering said instruction codes in accordance with a corresponding predetermined deciphering format, each decipherer having a different deciphering format producing different deciphering results for the same instruction codes and said at least two decipherers deciphering the corresponding type instructions in a one to one correspondence; and selecting means, operatively connected to said discriminating means and said at least two instruction decipherers, for selectively outputting the deciphered results from one of said at least two instruction decipherers in dependence upon the discrimination by said discrimination means.

Claim 18

An apparatus as recited in claim 11, wherein said at least two instruction decipherers include first and second decipherers, said addresses include odd and even addresses respectively, and said first decipherer deciphers odd address location instructions and said second decipherer deciphers even address location instructions in accordance with the least significant bit in the addresses.

Claim 19

An apparatus as recited in claim 11, wherein the microcomputer includes an instruction set and each decipherer, when provided with the enciphered instruction set, produces each one of the instructions of the instruction set.

Claim 20

A deciphering apparatus for a microcomputer capable of executing a plurality of types of instructions, the microcomputer including: a read only memory for storing a program having instructions of an instruction set, the program being constructed from a combination of first type instruction codes enciphered by a first enciphering format and second type instruction codes enciphered by a second enciphering format; a data bus connected to said read only memory; an address bus connected to said read only memory; a program counter, connected to said address bus, for generating an address to access said read only memory; and a control unit for generating control signals to control the microcomputer and external circuits; and said apparatus comprising: a first instruction decipherer, connected to said control unit, for supplying a deciphered instruction code, and capable of deciphering all of the first type instruction codes corresponding to said plurality of types of instructions, in a one to one correspondence; a second instruction decipherer, connected to said control unit, for supplying the deciphered instruction codes, and capable of deciphering all of the second type instruction codes correponding to said plurality of types of instructions in a one to one correspondence; a selecting circuit, connected between said data bus and said first and second instruction decipherers, for selectively supplying the output of said read only memory to one of said first and second instruction decipherers; and a discriminating circuit, connected between said address bus and said selecting circuit, for controlling said selecting circuit in response to a predetermined bit of the address, selected from among a least significant bit through a most significant bit, to supply the first or the second type instruction code read from said read only memory to a corresponding one of said first and second instruction decipherers; and whereby the program contructed from the combination of said first type instruction codes and said second type instruction codes is executed.

Claim 21

A deciphering apparatus for a microcomputer capable of executing a plurality of types of instructions, the microcomputer including: a read only memory for storing a program having instructions of an instruction set, the program being constructed from a combination of first type instruction codes enciphered by a first enciphering format and second type instruction codes enciphered by a second enciphering format; a data bus connected to said read only memory; an address bus connected to said read only memory; a program counter, connected to said address bus, for generating an address to access said read only memory; and a control unit for generating control signals to control the microcomputer and external circuits; and said apparatus comprising: a first instruction decipherer, connected to said control unit, for supplying a deciphered instruction code, and capable of deciphering all of the first type instruction codes corresponding to said plurality of types of instructions, in a one to one correspondence; a second instruction decipherer, connected to said control unit, for supplying the deciphered instruction codes, and capable of deciphering all of the second type instruction codes correponding to said plurality of types of instructions in a one to one correspondence; a selecting circuit, connected between said data bus and said first and second instruction decipherers, for selectively supplying the output of said read only memory to one of said first and second instruction decipherers; and a discriminating circuit, connected between said address bus and said selecting circuit, for controlling said selecting circuit in response to a predetermined bit of the address, selected from among a least significant bit through a most significant bit, to supply the first or the second type instruction code read from said read only memory to a corresponding one of said first and second instruction decipherers; and whereby the program contructed from the combination of said first type instruction codes and said second type instruction codes is executed.

Claim 22

A microcomputer as set forth in claim 14, wherein said discriminating circuit comprises means for generating a selecting signal from the predetermined bit of the address, and said selecting circuit comprises gate means, operatively connected to said means for generating the selecting signal and said first and second instruction decipherers, for transferring an instruction code to one of said first and second instruction decipherers, said selecting signal being supplied to said gate means to open or close said gate means.

Claim 23

A microcomputer as set forth in claim 14, wherein the deciphered results from said first and second instruction decipherers coincide with instructions of the instruction set to be performed by said microcomputer.

Claim 24

A microcomputer as set forth in claim 15, wherein said means for generating the selecting signal comprises a signal line, operatively connected between said program counter and said gate means, transferring the least significant bit of the address.

Claim 25

A microcomputer as set forth in claim 15, wherein said means for generating the selecting signal comprises a decoding circuit, operatively connected between said program counter and said gate means, for decoding the least significant bit of the address signal and providing a selection signal controlling said gate means.

Claim 26

An apparatus as recited in claim 14, wherein the microcomputer includes an instruction set and each decipherer, when provided with the enciphered instruction set, produces each one of the instructions of the instruction set.

Claim 27

A deciphering apparatus for a microcomputer capable of executing a plurality of types of instructions, said microcomputer including: a read only memory for storing a program having instructions of an instruction set, the program being constructed from a combination of first type instruction codes enciphered by a first enciphering format and second type instruction codes enciphered by a second enciphering format; a data bus connected to said read only memory; an address bus connected to said read only memory; a program counter, connected to said address bus, for generating an address to access said read only memory; and a control unit for generating control signals to control the microcomputer itself and external circuits; and said apparatus comprising: a first instruction decipherer, connected to said control unit, for supplying a deciphered instruction code, capable of deciphering all of the first type instruction codes corresponding to said plurality of types of instructions in a one to one correspondence; a second instruction decipherer, connected to said control unit, for supplying the deciphered instructions, capable of deciphering all of the second type instruction codes corresponding to said plurality of types of instructions in a one to one correspondence; a selecting circuit, connected between outputs of said first and second instruction decipherers and said control unit, for selectively outputting the deciphered results from one of said first and second instruction decipherers; and a discriminating circuit, connected between said address bus and said selecting circuit, for controlling said selecting circuit in response to a predetermined bit of the address, selected from among a least significant bit through a most significant bit, to supply the first or the second type instruction code read from said read only memory to a corresponding one of said first and second instruction decipherers; and whereby the program constructed from the combination of said first type instruction codes and said second type instruction codes is executed.

Claim 28

A deciphering apparatus for a microcomputer capable of executing a plurality of types of instructions, said microcomputer including: a read only memory for storing a program having instructions of an instruction set, the program being constructed from a combination of first type instruction codes enciphered by a first enciphering format and second type instruction codes enciphered by a second enciphering format; a data bus connected to said read only memory; an address bus connected to said read only memory; a program counter, connected to said address bus, for generating an address to access said read only memory; and a control unit for generating control signals to control the microcomputer itself and external circuits; and said apparatus comprising: a first instruction decipherer, connected to said control unit, for supplying a deciphered instruction code, capable of deciphering all of the first type instruction codes corresponding to said plurality of types of instructions in a one to one correspondence; a second instruction decipherer, connected to said control unit, for supplying the deciphered instructions, capable of deciphering all of the second type instruction codes corresponding to said plurality of types of instructions in a one to one correspondence; a selecting circuit, connected between outputs of said first and second instruction decipherers and said control unit, for selectively outputting the deciphered results from one of said first and second instruction decipherers; and a discriminating circuit, connected between said address bus and said selecting circuit, for controlling said selecting circuit in response to a predetermined bit of the address, selected from among a least significant bit through a most significant bit, to supply the first or the second type instruction code read from said read only memory to a corresponding one of said first and second instruction decipherers; and whereby the program constructed from the combination of said first type instruction codes and said second type instruction codes is executed.

Claim 29

An apparatus as recited in claim 20, wherein the microcomputer includes an instruction set and each decipherer, when provided with the enciphered instruction set, produces each one of the instructions of the instruction set.