On-chip microprocessor instruction decoder having hardware for selectively bypassing on-chip circuitry used to decipher encrypted instruction codes

Claim 1

A microprocessor formed on an integrated circuit and adapted to execute the instructions of a specific instruction set, each instruction in said set being defined by a prescribed, digital instruction code, said microprocessor comprising, in combination: (a) means, having a plurality of first inputs and responsive to said instruction codes applied to said first inputs, for executing the instructions defined by said instruction codes; (b) instruction code queuing means, having a plurality of first outputs each connected to one of said first inputs of said instruction executing means, for receiving, storing and applying successive instruction codes to said first inputs, said queuing means including a decoder means for translating enciphered instruction codes into said prescribed, digital instruction codes; and said decoder means including (1) deciphering means for converting instruction codes; and (2) bypassing means, connected to said deciphering means, for directing enciphered instruction codes through said deciphering means and directing non-enciphered instruction codes around said deciphering means and said bypassing means including switching means, arranged to receive instruction codes, for selecting a path for said instruction codes either to said deciphering means or around said deciphering means; and said switching means is responsive to said instruction codes for selecting said path.