Patent US4903267A successfully refreshed from Google Patents.
US4903267A
Expired / Lapsed
US
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Method of generating test data
Assignee: Hitachi Ltd
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Filing: 1987-11-30
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Granted: 1990-02-20
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Expires: 2007-11-30
Abstract
Abstract The invention prepares test data on a logic LSI which includes a plurality of signal pins, a control pin for inputting an external control signal, and control circuitry responsive to the external control signal for setting the signal pins in a desired state according to a specified function thereof. In accordance with the invention, the method comprises the steps of storing first data in a first memory, the first data being representative of a specified function of individual pins; storing the second data in a second memory, the second data representing a plurality of pin states corresponding to a plurality of signal states set by the external control signal; reading first and second data from the first and second memory; selectively communicating the test control signal to the integrated circuit, generating third data representative of each pin state of individual pins of each signal state set by the external control signal; and storing the third data into a file as test data.
Inventors
- 👤 Kiyokazu Arai
- 👤 Syun Ishiyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:34
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318307; G01R31/319; G01R31/31903; G01R31/31908
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
207 words
A method of generating operating test data for an integrated circuit having a plurality of signal pins having functions of input, output or input/output, a plurality of control pins for inputting an external test control signal, and means responsive to the external control signal for selectively setting each signal pin in a desired state, the method being applied to a test device having a first memory, a second memory, and a file, the method comprising the steps of: storing first data in the first memory, the first data being representative of the specific function of each individual signal pin; storing second data in the second memory, the second data being respresentative of a plurality of pin states corresponding to a plurality of signal states of the external test control signal, each pin state being predetermined in accordance with its pin function; reading the first and second data from the first and second memory; selectively communicating said external test control signal to the integrated circuit to be tested; generating third data representative of each pin state of signal pins of the integrated circuit to be tested corresponding to each signal state of the external test control signal; and storing the third data into a file as test data.
Claim 2
Independent Claim
207 words
A method of generating operating test data for an integrated circuit having a plurality of signal pins having functions of input, output or input/output, a plurality of control pins for inputting an external test control signal, and means responsive to the external control signal for selectively setting each signal pin in a desired state, the method being applied to a test device having a first memory, a second memory, and a file, the method comprising the steps of: storing first data in the first memory, the first data being representative of the specific function of each individual signal pin; storing second data in the second memory, the second data being respresentative of a plurality of pin states corresponding to a plurality of signal states of the external test control signal, each pin state being predetermined in accordance with its pin function; reading the first and second data from the first and second memory; selectively communicating said external test control signal to the integrated circuit to be tested; generating third data representative of each pin state of signal pins of the integrated circuit to be tested corresponding to each signal state of the external test control signal; and storing the third data into a file as test data.
Claim 3
Dependent Claim
47 words
The method of claim 1 wherein the signal pin includes an output pin, and wherein the generating step includes the step of producing data representative of which signal pin outputs a primary logic signal in an event when the external control signal is at a first state.
Claim 4
Dependent Claim
43 words
The method of claim 2 wherein the generating step includes the step of producing data representative of which signal pin outputs a secondary logic signal in an event when the external control signal is at a second state different from the first state.
Claim 5
Dependent Claim
53 words
The method of claim 3 wherein the signal pin includes an input pin, and wherein the generating step includes the step of producing data representative of which signal pin receives a logic signal in an event when the external control signal is at a third state different from the first and second state.
Claim 6
Dependent Claim
38 words
The method of claim 4 wherein the generating step includes the step of producing data representative of which signal pin receives a remaining logic signal in an event when the external control signal is at the third state.
Claim 7
Dependent Claim
68 words
The method of claim 5 wherein the method includes the steps of: reading the third data from the file; supplying the control pin with the first state external control signal; measuring voltage of the signal pin designated by the third data as that outputting the primary logic level; and comparing the voltage of the signal pin with a predetermined limit value to determine acceptability of the integrated circuit.
Claim 8
Dependent Claim
68 words
The method of claim 5 wherein the method includes the steps of: reading the third data from the file; supplying the control pin with the second state external control signal; measuring voltage of the signal pin designated by the third data as that outputting the secondary logic level; and comparing the voltage of the signal pin with a predetermined limit value to determine acceptability of the integrated circuit.
Claim 9
Dependent Claim
67 words
The method of claim 5 wherein the method includes the steps of: reading the third data from the file; supplying the one logic signal to signal pin designated by the third data as that to be supplied therewith; measuring current at the signal pin designated by the third data; and comparing the current with a predetermined limit value so as to determine acceptability of the integrated circuit.
Claim 10
Independent Claim
196 words
An apparatus for generating test data for an integrated circuit having a plurality of signal pins having functions of input, output or input/output, a plurality of control pins for inputting an external control signal, and means responsive to the external control signal for selectively setting each signal pin in a desired state according to a specified function thereof, the apparatus comprising: a first memory adapted for storing first data representative of the specified function of each individual pin; a second memory adapted for storing second data representative of a plurality of pin states corresponding to a plurality of signal states of the external control signal, each pin state being predetermined in accordance with its pin function; means for reading the first and second data from the first and second memory respectively; means for selectively communicating the external test control signal to the integrated circuit to be tested; means responsive to the first and second data for generating third data which represents each pin state of signal pins of the integrated circuit to be tested corresponding to each signal state of the external control signal; and file means for storing the third data as a test data.
Claim 11
Independent Claim
196 words
An apparatus for generating test data for an integrated circuit having a plurality of signal pins having functions of input, output or input/output, a plurality of control pins for inputting an external control signal, and means responsive to the external control signal for selectively setting each signal pin in a desired state according to a specified function thereof, the apparatus comprising: a first memory adapted for storing first data representative of the specified function of each individual pin; a second memory adapted for storing second data representative of a plurality of pin states corresponding to a plurality of signal states of the external control signal, each pin state being predetermined in accordance with its pin function; means for reading the first and second data from the first and second memory respectively; means for selectively communicating the external test control signal to the integrated circuit to be tested; means responsive to the first and second data for generating third data which represents each pin state of signal pins of the integrated circuit to be tested corresponding to each signal state of the external control signal; and file means for storing the third data as a test data.
Claim 12
Dependent Claim
80 words
The apparatus of claim 9 wherein the apparatus further comprises: means for reading the third data from the file means; means for supplying the control pin with a first state external control signal; means for measuring voltage of at least one of the signal pins designated by the third data as that outputting the one of logical level; and means for comparing the voltage of the signal pin with a predetermined limit value to determine acceptability of the integrated circuit.
Claim 13
Dependent Claim
74 words
The apparatus of claim 9 wherein the apparatus further comprises: means for reading the third data from the file means; means for supplying a logic signal to a signal pin designated by the third data as that which is to be supplied the level; means for measuring current of the signal pin designated by the third data; and means for comparing the current with a predetermined value to determine acceptability of the integrated circuit.
Claim 14
Independent Claim
244 words
A method of generating test data for an integrated circuit having a signal pin, a control pin for inputting an external control signal for setting each signal pin in a desired state according to a specified function thereof, the method being applied to a test device having a first memory, a second memory, a third memory, and a file, the method comprising the steps of: storing first data in a first memory, the first data representing specifications of individual pins; storing second data in a second memory, the second data respresenting a plurality of pin states corresponding to a plurality of signal states of the external control signal; storing third data in a third memory, the third data representing an electrical limit value of the integrated circuit; reading the first and second data from the first and second memory respectively; responsive to the first and second data, generating fourth data by means of the test device representative of each pin state of the signal pins of the integrated circuit to be tested corresponding to each signal state of the external test control signal; reading the third data from the third memory; responsive to the third and fourth data, producing fifth data by means of the test device which represents each pin state of individual signal pins and electrical limit values of the pin in each signal state of the external control signal; and storing the fifth data into a file as a test data.
Claim 15
Independent Claim
244 words
A method of generating test data for an integrated circuit having a signal pin, a control pin for inputting an external control signal for setting each signal pin in a desired state according to a specified function thereof, the method being applied to a test device having a first memory, a second memory, a third memory, and a file, the method comprising the steps of: storing first data in a first memory, the first data representing specifications of individual pins; storing second data in a second memory, the second data respresenting a plurality of pin states corresponding to a plurality of signal states of the external control signal; storing third data in a third memory, the third data representing an electrical limit value of the integrated circuit; reading the first and second data from the first and second memory respectively; responsive to the first and second data, generating fourth data by means of the test device representative of each pin state of the signal pins of the integrated circuit to be tested corresponding to each signal state of the external test control signal; reading the third data from the third memory; responsive to the third and fourth data, producing fifth data by means of the test device which represents each pin state of individual signal pins and electrical limit values of the pin in each signal state of the external control signal; and storing the fifth data into a file as a test data.
Claim 16
Dependent Claim
32 words
The method of claim 12 wherein the generating step includes the step of generating sixth data representative of desired signal pin output when the external control signal is at a first state.
Claim 17
Dependent Claim
29 words
The method of claim 13 wherein the producing step includes the step of producing data representative of a desired voltage limit of the pin designated by the sixth data.
Claim 18
Dependent Claim
42 words
The method of claim 12 wherein the generating step includes the step of generating seventh data representative of which signal pin is to be supplied a logic level when a signal state of the external control signal is at a second state.
Claim 19
Dependent Claim
32 words
The method of claim 15 wherein the producing step includes the step of producing data representative of a limit current to be supplied to the signal pin designated by the seventh data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-19 | 1993-08-21 | 1994-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-19 | 1997-08-21 | 1998-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-19 | 2001-08-21 | 2002-02-20 | $7700.00 | Window Closed / Lapsed |