Semiconductor memory device having a register

Claim 2

A semiconductor memory device having a register comprising: a memory cell array having memory cells; a data bus; input/output means provided between the memory cell array and the corresponding data bus; register means for storing predetermined data; transfer gate means being connected between the data bus and the register means; first data buffer means for transferring data on the data bus to an external circuit; second data buffer means for transferring data derived from the external circuit to the data bus; and controlling means for disconnecting the input/output means from the data bus and turning OFF the transfer gate means in a first operation mode and for connecting the input/output means to the data bus and turning ON the transfer gate means in a second operation mode, wherein in the first operation mode, one of a data read operation and write operation is performed between the memory cell array and the external circuit via the data bus and either one of the first and second buffer means, and alternatively in the second operation mode one of the data read operation and write operation is performed between the register means and the external circuit via the transfer gate means, the data bus and either one of the first and second buffer means.

Claim 3

A semiconductor memory device as claimed in claim 1, wherein the register means comprises a register for storing color data which is to be written into the memory cell array.

Claim 4

A semiconductor memory device as claimed in claim 1, wherein the register means comprises a mask register for storing mask data for disactivating the second data buffer means per one bit unit.

Claim 5

A semiconductor memory device as claimed in claim 1, wherein the register means comprises a plurality of registers, and the transfer gate means is provided for each of the plurality of registers, and wherein any one of the plurality of registers is connected to the data bus by turning ON the corresponding transfer gate means in response to a part of an address to be supplied to the memory cell array.

Claim 6

A semiconductor memory device as claimed in claim 1, wherein the controlling means comprises mode discrimination means for producing a first operation mode setting signal which instructs the setting of the first operation mode and a second operation mode setting signal which instructs the setting of the second operation mode in response to a predetermined signal supplied from the external circuit, register decoder means for producing a control signal used for controlling ON/OFF of the transfer gate means in response to a part of an address which is to be supplied to the memory cell array, and means for controlling connection and disconnection between the input/output means and the data bus in response to the second operation mode setting signal and the first operation mode setting signal which are produced by the mode discriminating means.

Claim 7

A semiconductor memory device as claimed in claim 5, wherein the means for controlling connection and disconnection produces a control signal which varies depending on which one of the first operation mode and the second operation mode is selected, and wherein the input/output means comprises an AND gate which is connected to the data bus and functions an address decoder with respect to the memory cell array, and wherein the means for controlling connection and disconnection produces the control signal such that the AND gate is disactivated when the second operation mode is selected, and wherein the means for controlling connection and disconnection produces the control signal such that the AND gate is activated when the first operation mode signal is selected.

Claim 8

A semiconductor memory device as claimed in claim 1, wherein the register means stores data consisting of a plurality of bits, and wherein the second data buffer means comprises a plurality of selectors for selecting one of data supplied from the external circuit and data supplied from the register means in accordance with the selected operation mode, and write amplifiers each provided for the respective selectors and connected to the data bus for amplifying output signals of the corresponding selectors.

Claim 9

A semiconductor memory device as claimed in claim 7, wherein the selectors select the data supplied from the register means in the second operation mode.

Claim 10

A semiconductor memory device having a register comprising: a plurality of memory cell arrays each having memory cells; a plurality of data buses each provided for the respective memory cell arrays; a plurality of input/output means each provided between the respective memory cell arrays and data buses; register means connected to any one of the plurality of data buses for storing predetermined data; transfer gate means being connected between the register means and the data bus to which the register means is connected; a plurality of first data buffer means each provided for the respective memory cell arrays for transferring data on the respective buses to an external circuit; a plurality of second data buffer means each provided for the respective memory cell arrays for transferring data derived from the external circuit to the respective data buses; and controlling means for disconnecting the input/output means from the data bus to which the transfer gate means is connected and turning OFF the transfer gate means in a first operation mode and for connecting the input/output means to the data bus and turning ON the transfer gate means in a second operation mode, wherein in the first operation mode, one of a data read operation and write operation is performed between the memory cell arrays and the external circuit, and alternatively in the second operation mode one of the data read operation and write operation is performed between the register means and the external circuit.

Claim 11

A semiconductor memory device having a register comprising: a plurality of memory cell arrays each having memory cells; a plurality of data buses each provided for the respective memory cell arrays; a plurality of input/output means each provided between the respective memory cell arrays and data buses; register means connected to any one of the plurality of data buses for storing predetermined data; transfer gate means being connected between the register means and the data bus to which the register means is connected; a plurality of first data buffer means each provided for the respective memory cell arrays for transferring data on the respective buses to an external circuit; a plurality of second data buffer means each provided for the respective memory cell arrays for transferring data derived from the external circuit to the respective data buses; and controlling means for disconnecting the input/output means from the data bus to which the transfer gate means is connected and turning OFF the transfer gate means in a first operation mode and for connecting the input/output means to the data bus and turning ON the transfer gate means in a second operation mode, wherein in the first operation mode, one of a data read operation and write operation is performed between the memory cell arrays and the external circuit, and alternatively in the second operation mode one of the data read operation and write operation is performed between the register means and the external circuit.

Claim 12

A semiconductor memory device as claimed in claim 9, wherein the register means comprises a plurality of registers each storing a predetermined number of bits, and the transfer gate means comprises a plurality of transfer gates each provided for the respective registers.

Claim 13

A semiconductor memory device as claimed in claim 10, wherein each of the plurality of the second buffer means comprises a plurality of selectors for selecting one data bit from among a predetermined data bit contained in the data supplied from the external circuit and a predetermined data bit contained in the data stored in each of the registers, and write amplifiers each provided for the respective selectors and connected to the respective data buses for amplifying output signals of the corresponding selectors.

Claim 14

A semiconductor memory device as claimed in claim 11, wherein each of the selectors selects one data bit among the data bits supplied from the registers.

Claim 15

A semiconductor memory device as claimed in claim 11, wherein each of the selectors selects one data bit among the data bits supplied from the registers in accordance with a value of the data bit supplied from the external circuit and applied to each selector.

Claim 16

A semiconductor memory device as claimed in claim 11, wherein the plurality of registers contains a mask register for storing a predetermined number of mask data bits, and the mask data bits stored in the mask register are supplied to the corresponding write amplifiers provided in each of the plurality of second data buffer means.

Claim 17

A semiconductor memory device as claimed in claim 9, wherein the controlling means comprises mode discrimination means for producing a first operation mode setting signal which instructs the setting of the first operation mode and a second operation mode setting signal which instructs the setting of the second operation mode in response to a predetermined signal supplied from the external circuit, register decoder means for producing a control signal used for controlling ON/OFF of the transfer gate means in response to a part of an address which is to be supplied to the memory cell array, and means for controlling connection and disconnection between the input/output means and the data bus in response to the second operation mode setting signal and the first operation mode setting signal which are produced by the mode discriminating means.

Claim 18

A semiconductor memory device as claimed in claim 15, wherein the means for controlling connection and disconnection produces a control signal which varies depending on which one of the first operation mode and the second operation mode is selected, and wherein the input/output means comprises an AND gate which is connected to the data bus and functions an address decoder with respect to the memory cell array, and wherein the means for controlling connection and disconnection produces the control signal such that the AND gate is disactivated when the second operation mode is selected, and wherein the means for controlling connection and disconnection produces the control signal such that the AND gate is activated when the first operation mode signal is selected.

Claim 19

A semiconductor memory device as claimed in claim 9, wherein the memory device is a memory device for image processing.