Semiconductor memory device with shift registers for high speed reading and writing

Claim 2

A semiconductor memory device comprising: a random-access memory having a memory cell array, a plurality of bit lines, and a plurality of word lines intersecting said plurality of bit lines; first and second shift registers, respectively, operatively connected to said plurality of bit lines; first and second transfer gate means operatively connected between said plurality of bit lines and said first and second shift registers, respectively; and parallel data transfer means, operatively connected between said first and second shift registers, for carrying out a parallel data transfer between said first and second shift registers independently of said first and second transfer gate means.

Claim 3

A device according to claim 1, wherein said parallel data transfer means comprises logic gates for effecting logic processing of the data to be transferred.

Claim 4

A device according to claim 2, wherein said logic gates are exclusive OR gates.

Claim 5

A device according to claim 3, wherein said logic gates include a plurality of input terminals, and wherein an additional shift register is connected to one of said input terminals of each of said logic gates.

Claim 6

A semiconductor memory device operatively connected to receive data from an external data source comprising: a random-access memory having a memory cell array including memory cells, a plurality of bit lines, and a plurality of word lines intersecting said plurality of bit lines; an output shift register, operatively connected to said random-access memory, data from one of a selected one of said word lines being input in parallel into said output shift register and being serially output from said output shift register; an input shift register for inputting data supplied serially from the external data source to a selected one of said word lines; parallel data transfer means, operatively connected to said input shift register and said output shift register, for carrying out logic processing of the data in said output shift register and said input shift register; and an instruction decoder, operatively connected to said parallel data transfer means, for delivering an instruction for a selected logic operation to be executed in said parallel data transfer means; the data for one of said word lines supplied to said input shift register and the instruction for instructing a selected logic operation being serially transmitted; the data for one word line output from said parallel data transfer means according to said instruction for a selected logic operation being written into said memory cells of a selected one of said word lines in said memory cell array.

Claim 7

A semiconductor memory device operatively connected to receive data from an external data source comprising: a random-access memory having a memory cell array including memory cells, a plurality of bit lines, and a plurality of word lines intersecting said plurality of bit lines; an output shift register, operatively connected to said random-access memory, data from one of a selected one of said word lines being input in parallel into said output shift register and being serially output from said output shift register; an input shift register for inputting data supplied serially from the external data source to a selected one of said word lines; parallel data transfer means, operatively connected to said input shift register and said output shift register, for carrying out logic processing of the data in said output shift register and said input shift register; and an instruction decoder, operatively connected to said parallel data transfer means, for delivering an instruction for a selected logic operation to be executed in said parallel data transfer means; the data for one of said word lines supplied to said input shift register and the instruction for instructing a selected logic operation being serially transmitted; the data for one word line output from said parallel data transfer means according to said instruction for a selected logic operation being written into said memory cells of a selected one of said word lines in said memory cell array.

Claim 8

A semiconductor memory device connected to an external data source providing external data and operatively connected to receive instructions for selecting a logic function, comprising: a random-access memory including: a memory cell array having a plurality of memory cells; bit lines; and word lines intersecting said bit lines; decoder means, operatively connected to receive the instructions, for decoding the instructions for selecting a logic function and outputting said decoded instructions; an input shift register, operatively connected to said external data source, for inputting external data supplied serially from the external data source to said word lines; an output shift register, operatively connected to said memory cell array and said input shift register, data for one of said word lines being input in parallel to said output shift register and being output in serial to an external circuit; and parallel data transfer means, operatively connected to said decoder means and between said input and output shift registers, for performing a selected logic processing on said data transferred from said input shift register to said output shift register in accordance with said decoded instructions output from said decoder means.

Claim 9

A semiconductor memory device connected to an external data source providing external data and operatively connected to receive instructions for selecting a logic function, comprising: a random-access memory including: a memory cell array having a plurality of memory cells; bit lines; and word lines intersecting said bit lines; decoder means, operatively connected to receive the instructions, for decoding the instructions for selecting a logic function and outputting said decoded instructions; an input shift register, operatively connected to said external data source, for inputting external data supplied serially from the external data source to said word lines; an output shift register, operatively connected to said memory cell array and said input shift register, data for one of said word lines being input in parallel to said output shift register and being output in serial to an external circuit; and parallel data transfer means, operatively connected to said decoder means and between said input and output shift registers, for performing a selected logic processing on said data transferred from said input shift register to said output shift register in accordance with said decoded instructions output from said decoder means.