US4584673A
Expired / Lapsed
US
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Series/parallel/series shift register memory system
Assignee: US Philips Corp
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Filing: 1983-06-06
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Granted: 1986-04-22
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Expires: 2003-06-06
Abstract
Abstract A series/parallel/series shift register memory system having storage positions provided on a substrate. In addition to the single parallel-connected storage registers required to achieve the nominal storage capacity, there are provided groups of first and second nominally redundant single storage registers. The first redundant registers are used as substitutes for faulty single storage registers, so that the nominal storage capacity can be maintained. The second redundant registers are used for the transport of redundant code data. Also provided is a multi-state sequencer for indicating, in each state, the information to be carried by a particular group of storage registers and for forming, on the basis of this information, an error-detecting or error correction code which is carried by the second redundant storage registers. Faulty storage registers can thus be pin-pointed, after which dummy information is automatically inserted in the input information at locations which are such that it will nominally be carried by the faulty registers, thus effectively substituting a first redundant register for each faulty register. The system is thus self-healing.
Inventors
- 👤 Karel E. Kuijk
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:48
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/86; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
473 words
A series/parallel/series shift register memory system comprising (a) a substrate on which are provided data storage positions configured to form a series input register having a serial data input, a series output register having a serial data output, and a plurality of single storage registers which link data outputs of respective stages of the series input register to data inputs of respective stages of the series output register to thereby form a parallel storage register between the series input and output registers, and (b) a transfer control device for repetitively supplying said registers with a sequence of shift signals, each sequence being such as to shift data presented to said serial data input into the series input register, to shift data present in said respective stages of the series input register in parallel into the parallel storage register, to shift data present at the output of the parallel storage register in parallel into said respective stages of the series output register, and to shift data present in the series output register to said serial data output, characterized in that it includes: (c) a multi-state sequencer provided with means for changing the state thereof in synchronism with the occurrence of successive said sequences, said sequencer, in each state thereof, (i) selecting particular data from that which is presented to the serial data input and causing the total data presented to the serial data input to be supplemented with redundant data in such manner that said redundant data will be transferred to the serial data output via a different said single storage register or registers to that or those via which the selected data will be transferred, said redundant data forming an error-detection code in conjunction with the selected data, (ii) selecting from the data appearing at the serial data output both redundant data which has previously been applied to the serial data input and the particular data in conjunction with which this redundant data forms an error-detection code and determining therefrom whether an error has occurred in respect of the selected data, and (iii) storing indicator information in an indicator memory in response to a determination or determinations that such an error has occurred, said indicator information indicating via which said single storage register or registers the data which is in error has been transferred, and (d) means for (i) supplementing the data applied to the serial data input with dummy information in response to the presence of such indicator information in the indicator memory so that any single storage register indicated by said indicator information will be supplied only with this dummy information and (ii) processing the data appearing at said serial data output in accordance with the content of the indicator memory so as to remove therefrom any which has been transferred via a single storage register indicated by said indicator information.
Claim 2
Dependent Claim
473 words
A series/parallel/series shift register memory system comprising (a) a substrate on which are provided data storage positions configured to form a series input register having a serial data input, a series output register having a serial data output, and a plurality of single storage registers which link data outputs of respective stages of the series input register to data inputs of respective stages of the series output register to thereby form a parallel storage register between the series input and output registers, and (b) a transfer control device for repetitively supplying said registers with a sequence of shift signals, each sequence being such as to shift data presented to said serial data input into the series input register, to shift data present in said respective stages of the series input register in parallel into the parallel storage register, to shift data present at the output of the parallel storage register in parallel into said respective stages of the series output register, and to shift data present in the series output register to said serial data output, characterized in that it includes: (c) a multi-state sequencer provided with means for changing the state thereof in synchronism with the occurrence of successive said sequences, said sequencer, in each state thereof, (i) selecting particular data from that which is presented to the serial data input and causing the total data presented to the serial data input to be supplemented with redundant data in such manner that said redundant data will be transferred to the serial data output via a different said single storage register or registers to that or those via which the selected data will be transferred, said redundant data forming an error-detection code in conjunction with the selected data, (ii) selecting from the data appearing at the serial data output both redundant data which has previously been applied to the serial data input and the particular data in conjunction with which this redundant data forms an error-detection code and determining therefrom whether an error has occurred in respect of the selected data, and (iii) storing indicator information in an indicator memory in response to a determination or determinations that such an error has occurred, said indicator information indicating via which said single storage register or registers the data which is in error has been transferred, and (d) means for (i) supplementing the data applied to the serial data input with dummy information in response to the presence of such indicator information in the indicator memory so that any single storage register indicated by said indicator information will be supplied only with this dummy information and (ii) processing the data appearing at said serial data output in accordance with the content of the indicator memory so as to remove therefrom any which has been transferred via a single storage register indicated by said indicator information.
Claim 3
Dependent Claim
59 words
A system as claimed in claim 1, wherein the said particular data selected in the successive states of the multi-state sequencer is such that each said single storage register via which the said total data is transferred to the serial data output transfers an item of said particular data when the sequencer is in at least one said state.
Claim 4
Dependent Claim
18 words
A system as claimed in claim 1 or claim 2, wherein the error-detection code is an error-correction code.
Claim 5
Dependent Claim
15 words
A system as claimed in claim 3, wherein the code is a majority decision code.
Claim 6
Independent Claim
19 words
A system as claimed in claims 1 or 2, wherein the storage positions are storage positions for magnetic bubbles.
Claim 7
Independent Claim
21 words
A system as claimed in any of claims 1 or 2, wherein the storage positions together form a charge transfer device.
Claim 8
Dependent Claim
23 words
A combination of a plurality of systems as claimed in claims 1 or 2 having a single said transfer control device in common.
Claim 9
Dependent Claim
22 words
Display apparatus including a picture memory system constituted by a series/parallel/series memory system or combination as claimed in claims 1 or 2.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-21 | 1989-10-21 | 1990-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-21 | 1993-10-21 | 1994-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-21 | 1997-10-21 | 1998-04-22 | $7700.00 | Window Closed / Lapsed |