Patent US3115044A successfully refreshed from Google Patents.
Patent US3916388A successfully refreshed from Google Patents.
Patent US4899071A successfully refreshed from Google Patents.
US4899071A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Active delay line circuit
Assignee: Standard Microsystems LLC
•
Filing: 1988-08-02
•
Granted: 1990-02-06
•
Expires: 2008-08-02
Abstract
Abstract A digital delay circuit that can be readily implemented in an integrated circuit is disclosed. The circuit includes a reference clock and two or more arrays of controlled delay elements. The reference clock is passed through one array of delay elements and the thus-delayed clock is compared to an undelayed clock in a phase detector or comparator the output of which is a control voltage. The latter is applied to the control inputs of each of the delay elements. The controlled delay elements may be in the form of buffers in which the delay is varible and controlled by the level of the control input.
Inventors
- 👤 Lou Morales
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:51
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03K; H03K5/00; H03K5/13; H03K5/133; H03K5/135; H03L7/081; H03L7/0812; H03L7/0816; H03K2005/00013; H03K2005/0015; H03K2005/00195
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
159 words
A digital delay circuit comprising a first and a second array of an integral number N and M of series-connected controllable delay elements, respectfully, each of said delay elements being characterized in that the delay established between its input and output is controlled by a control signal applied to a control input thereat, a source of a reference clock, means for delaying said reference clock through one of said first and second arrays of delay elements, thereby to establish a delayed reference clock, means coupled to said clock source and to said first array of delay elements for comparing said reference clock and said delayed reference clock to produce a control signal representative of the comparison between said reference clock and said delayed reference clock, and means for applying said control signal to the control input of each of said controllable delay elements, thereby to vary the delay introduced by each of said delay elements to an input signal.
Claim 2
Dependent Claim
159 words
A digital delay circuit comprising a first and a second array of an integral number N and M of series-connected controllable delay elements, respectfully, each of said delay elements being characterized in that the delay established between its input and output is controlled by a control signal applied to a control input thereat, a source of a reference clock, means for delaying said reference clock through one of said first and second arrays of delay elements, thereby to establish a delayed reference clock, means coupled to said clock source and to said first array of delay elements for comparing said reference clock and said delayed reference clock to produce a control signal representative of the comparison between said reference clock and said delayed reference clock, and means for applying said control signal to the control input of each of said controllable delay elements, thereby to vary the delay introduced by each of said delay elements to an input signal.
Claim 3
Dependent Claim
49 words
The digital delay circuit of claim 1, in which each of said delay elements comprises an input voltage control section receiving the control signal and producing first and second control voltages, a plurality of series-connected CMOS inverters the input of the first of said inverters receiving an input signal.
Claim 4
Dependent Claim
51 words
The digital delay circuit of claim 2, in which each of said inverters is connected in series with complementary first and second MOS control devices between a voltage source and a reference potential, the gates of said first and second MOS control devices respectively receiving said first and second control voltages.
Claim 5
Dependent Claim
49 words
The digital delay circuit of claim 1, further comprising means for deriving the true and complement of the clock signal, and gating means interposed intermediate said clock deriving means and said comparing means for respectively receiving one of the true and complement clock signals and said delayed reference clock.
References Cited (Backward Citations)
US3737673A
Cited
US3914702A
Cited
US3855549A
Cited
US4532439A
Cited
EP0171022A2
Cited
US4700089A
Cited
US4837466A
Cited
US4771196A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-05 | 1993-08-07 | 1994-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-05 | 1997-08-07 | 1998-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-05 | 2001-08-07 | 2002-02-06 | $7700.00 | Window Closed / Lapsed |