Signal delay device

Claim 2

A signal delay device comprising: CMOS gate circuit means having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages from operation power voltage sources are applied; and voltage control means inserted in a power supplying path for said CMOS gate circuit means in association with at least one MOS-FET of said CMOS gate circuit means for controlling voltage applied to said CMOS gate circuit means, a control signal being applied to said voltage control means for the control of the applied voltage; the voltage applied to said CMOS gate circuit means being controlled in response to the control signal applied to said voltage control means and a period of delay in a signal between said input and output terminals of said CMOS gate circuit means thereby being controlled.

Claim 3

A signal delay device as defined in Claim 1 wherein said voltage control means comprises MOS-FET means whose drain and source circuit is inserted in series in a current path of said CMOS gate circuit means and the control signal is applied to a gate circuit of said MOS-FET.

Claim 4

A signal delay device as defined in Claim 1 wherein said CMOS gate circuit means comprises CMOS gates connected in series in plural stages, common operation power voltages being applied to the respective CMOS gates.

Claim 5

A signal delay device as defined in Claim 2 wherein said MOS-FET means comprises a plurality of MOS-FET's connected in parallel between said power voltage supply terminal and said operation power voltage source, separate control signals being applied to gates of the respective MOS-FET's to control them separately.

Claim 6

A signal delay device as defined in Claim 2 wherein said MOS-FET means comprises a plurality of MOS-FET's connected in series between said power voltage supply terminal and said operation power voltage source, separate control signals being applied to gates of the respective MOS-FET's to control them separately.

Claim 7

A signal delay device as defined in Claim 2 wherein said MOS-FET means comprises a MOS-FET inserted between a MOS-FET of said CMOS gate circuit means and said output terminal.

Claim 8

A signal delay device as defined in Claim 6 wherein said C MOS gate circuit means includes CMOS gates connected in series in plural stages, a plurality of MOS-FET's constituting said voltage control means are provided in correspondence to said CMO S gates and are controlled by common control signal applied to the gates of said MOS-FET's, and said voltage control means further comprises MOS-FET inserted between said power voltage supply terminal and said operation power voltage source and controlled by control signal which is applied to a gate thereof and is different from said common control signals.

Claim 9

A signal delay device as defined in Claim 1 wherein said voltage control means comprises: first and second registor means connected respectively between sources of first and second MOS-FET's constituting said CMOS gate circuit means and the operation power voltage sources connected to the MOS-FET's; a third MOS-FET whose drain-source path is connected between a junction of said first resistor means and the operation power voltage source therefor and the source of said second MOS-FET; and a fourth MOS-FET whose drain-source path is connected between a junction of said second registor means and the operation voltage source therefor and the source of said first MOS-FET; said control signal being applied to gates of said third and fourth MOS-FET's.

Claim 10

A signal delay device as defined in Claim 1 wherein said voltage control means comprises: a third MOS-FET connected between one of first and second MOS-FET's constituting said CMOS gate circuit means and said output terminal; a fourth MOS-FET inserted between the source of said one of the MOS-FET's and said operation power voltage source; and said control signal being applied to gates of said third and fourth MOS-FET's.

Claim 11

A ring oscillator including the signal delay device as defined in Claim 1 further comprising: reference frequency signal generation means for generating a reference signal of a constant frequency; comparator means for comparing in phase the reference signal with the output signal of said ring oscillator; and control voltage generation means for generating a control voltage corresponding to a result of comparison in said comparator means and applying the generated control voltage to said voltage control means of said signal delay device of the ring oscillator; the application of said control voltage constituting a phase-locked loop so as to stabilize the frequency of the output of the ring oscillator.

Claim 12

A pulse count detection circuit including the signal delay device as defined in Claim 1 further comprising: reference voltage generation means for generating a reference signal of a constant voltage; comparator means for comparing the reference signal with the output signal of said pulse count detection circuit; and control voltage generation means for generating a control voltage corresponding to a result of comparison in said comparator means and applying the generated control voltage to said voltage control means of said signal delay device of the pulse count detection circuit; the application of said control voltage constituting a negative feedback loop so as to stabilize the pulse width of the output signal of said pulse count detection circuit.

Claim 13

A circuit as defined in Claim 10 or 11 further comprising a CMOS gate circuit consisting of CMOS gates connected in series in plural stages and operating as a signal delaying circuit, said control voltage from said control voltage generation means being supplied also to said CMOS gate circuit as its operation power voltage.

Claim 14

A circuit as defined in Claim 12 wherein said CMOS gates of the CMOS gate circuit and the MOS-FET's of said CMOS gate circuit means are formed on a same substrate under a same environment.

Claim 15

A circuit as defined in Claim 10 or 11 further comprising a CMOS gate circuit consisting of CMOS gates connected in series in a loop in an odd number of stages operating as an oscillator for producing an oscillation output from a predetermined output of said CMOS gates, said control voltage from said control voltage generation means being supplied also to the CMOS gate circuits as its operation power voltage.

Claim 16

A circuit as defined in Claim 14 wherein said CMOS gates of the CMOS gate circuit and the MOS-FET's of said CMOS gate circuit means are formed on a same substrate under a same environment.

Claim 17

A circuit as defined in Claim 10 or 11 further comprising: a CMOS gate circuit consisting of CMOS gates connected in series in an even number of stages; an exclusive OR gate receiving input and output signals of said CMOS gate circuit; and a low-pass filter circuit connected to the output of said exclusive OR gate; said CMOS gate circuit, exclusive OR gate and low-pass filter circuit operating as a pulse count detection circuit and said control voltage from said control voltage generation means being supplied also to said CMOS gate circuit as its operation power voltage.

Claim 18

A circuit as defined in Claim 16 wherein said CMOS gates of the CMOS gate circuit and the MOS-FET's of said CMOS gate circuit means are formed on a same substrate under a same environment.

Claim 19

A circuit as defined in Claim 10 or 11 further comprising a CMOS gate circuit consisting of CMOS gates connected in series in plural stages in a loop, said CMOS gate circuit operating as a frequency modulation circuit with an input signal being applied to modulate the operation power voltage of said CMOS gate circuit and a modulated output being derived from a predetermined output of said CMOS gates; and said control voltage from said control voltage generation means being supplied also to said CMOS gate circuit as its operation power voltage.

Claim 20

A circuit as defined in Claim 18 wherein said CMOS gates of the CMOS gate circuit and the MOS-FET's of said CMOS gate circuit means are formed on a same substrate under a same environment.

Claim 21

An analog signal delay circuit including the signal delay device as defined in Claim 1 further comprising: a frequency modulation circuit receiving an analog signal to be delayed, pulse frequency-modulating the analog signal, outputting and supplying the frequency-modulated signal to said signal delay device; and a frequency demodulation circuit receiving the output signal of said frequency modulation circuit having been delayed by said signal delay device and pulse frequency-demodulating the received signal, the output signal of said frequency demodulation circuit constituting a delayed analog signal of the analog input signal.

Claim 22

A circuit as defined in Claim 20 wherein said CMOS gates of the CMOS gate circuit and the MOS-FET's of said CMOS gate circuit means are formed on a same substrate under a same environment.

Claim 23

An analog signal delay circuit as defined in Claim 20 wherein said frequency modulation circuit comprises a CMOS gate circuit consisting of CMOS gates connected in series in a loop in plural stages operating as a ring oscillator, the analog signal to be delayed being applied to said CMOS gate circuit to modulate an operation power voltage of said CMOS gate circuit and the frequency-modulated signal being derived from a predetermined output of said CMOS gates.

Claim 24

An analog signal delay circuit as defined in Claim 20 wherein said frequency demodulation circuit comprises: a C M OS gate circuit consisting of CMOS gates connected in series in plural stages receiving the output signal of said frequency modulation circuit having been delayed by said signal delay device; an exclusive OR gate receiving input and output signals of said CMOS gate circuit; and a low-pass filter circuit connected to the output of said exclusive OR gate, the output of said low-pass filter circuit being derived as the delayed analog signal.

Claim 25

A circuit as defined in Claim 23 wherein said CMOS gates of the CMCS gate circuit and the MOS-FET's of said CMOS gate circuit means are formed on a same substrate under a same environment.

Claim 26

An analog signal delay circuit as defined in Claim 20 further comprising: a ring oscillator including a CMOS gate circuit consisting of CMOS gates connected in series in a loop in a plural stages and producing an oscillation output from a predetermined output of said CMOS gates; reference frequency signal generation means for generating a reference signal of a constant frequency; comparator means for comparing in phase the reference signal with the output signal of said ring oscillator; and control voltage generation means for generating a control voltage corresponding to a result of comparison in said comparator means and applying the generated control voltage to said CMOS gate circuit of the ring oscillator as its operation power voltage; the application of said control voltage constituting a phase-locked loop so as to stabilize the frequency of the output signal of the ring oscillator and said control voltage being supplied to the CMOS gate circuits of said frequency modulation circuit, signal delay device and frequency demodulation circuit; and the CMOS gate circuits of said ring oscillator, frequency modulation circuit, signal delay device and frequency demodulation circuit being disposed under the same temperature condition.

Claim 27

A jitter absorption circuit in a recorded signal playback device including the signal delay device as defined in-Claim 1 wherein: a reproduced signal from a recording medium is derived through said signal delay device; said jitter absorption circuit further comprises a circuit for reproducing time axis data of said reproduced signal; and the delay time in said signal delay device is controlled by an output signal of said time axis data reproducing circuit in such a manner that the delay time is prolonged when the reproduced signal is ahead of a reference position in the time axis direction and the delay time is shortened when the reproduced signal is delayed from the reference position whereby jitter in the reproduced signal is absorbed.

Claim 28

A jitter absorption circuit as defined in Claim 26 wherein said recording medium is an optical type video disc and said recorded signal playback device is an optical type video disc player.

Claim 29

A jitter absorption circuit as defined in Claim 27 further comprising: a second signal delay device connected after said first signal delay device; a color burst signal reproducing circuit for extracting a color burst signal from the reproduced signal from the recording medium; a delay time in said second signal delay device being controlled in response to the color burst signal obtained by the color burst signal reproducing circuit.

Claim 30

A jitter absorption circuit as defined in Claim 27 wherein: a pickup head for generating the reproduced signal from the recording medium is fixed in a tangential direction of the recording medium without mechanical control in the tangential direction.

Claim 31

A jitter absorption circuit in an optical video disc playback device comprising: a pickup head for generating a reproduced signal from an optical video disc as a recording medium, the pickup head being fixed in a tangential direction of.the video disc without mechanical control in the tangential directicn; a signal delay device for time-delaying the reproduced signal from the pickup head; and a time axis data reproducing circuit for reproducing time axis data of said reproduced signal; a delay time in said signal delay device being controlled in response to an output signal of said time axis data reproducing circuit in such a manner that the delay time is prolonged when the reproduced signal is ahead of a reference position in the time axis direction and the delay time is shortened when the reproduced signal is delayed from the reference position whereby jitter in the reproduced signal is absorbed.

Claim 32

A jitter absorption circuit in an optical video disc playback device comprising: a pickup head for generating a reproduced signal from an optical video disc as a recording medium, the pickup head being fixed in a tangential direction of.the video disc without mechanical control in the tangential directicn; a signal delay device for time-delaying the reproduced signal from the pickup head; and a time axis data reproducing circuit for reproducing time axis data of said reproduced signal; a delay time in said signal delay device being controlled in response to an output signal of said time axis data reproducing circuit in such a manner that the delay time is prolonged when the reproduced signal is ahead of a reference position in the time axis direction and the delay time is shortened when the reproduced signal is delayed from the reference position whereby jitter in the reproduced signal is absorbed.

Claim 33

A jitter absorption circuit as defined in Claim 26 wherein said recording medium is a Compact Disc in the Compact Disc Digital Audio System and said recorded signal playback device is a Compact Disc player in the Compact Disc Digital Audio System.

Claim 34

A fixed head type magnetic tape reproducing device including the signal delay device as defined in Claim 1 wherein: said signal delay device is provided for a reproduced signal channel of each track; said reproducing device further comprises a detection circuit for detecting a synchronizing error between reproduced signals from respectige tracks; and the delay time of said signal delay device is controlled in response to the synchronizing error detected by said detection circuit whereby reproduced signals which are synchronized between the respective tracks are derived.