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US4897840A
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Method and apparatus for controlling the error correction within a data transmission controller given data read from moving peripheral storages, particularly disk storages, of a data processing system
Assignee: Wincor Nixdorf International GmbH
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Filing: 1988-03-10
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Granted: 1990-01-30
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Expires: 2008-03-10
Abstract
Abstract In order to reduce the time losses that arise when reading a plurality of successive data blocks, because of the interruption of the read operation in the case of recognized data errors, all required data blocks are read in one pass and are transferred into a correspondingly enlarged buffer memory (DAT-SP). Error syndromes (ES) resulting from the recognized data errors are initially intermediately stored in allocation to the erroneous data, until a correction of the data in the data memory (DAT-SP) is possible.
Inventors
- 👤 Eckardt Weiss
- 👤 Peter Wentzel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 04:34
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1833; G06F3/0628; G06F3/0655; G06F3/0656
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
234 words
A method for controlling error correction within a data transmission controller, said transmission controller controlling the transmission of data from a disk storage device to a data processing system, said data being recorded in said disk storage device in a plurality of blocks with check characters, said method comprising the steps of: providing a buffer memory for intermediately storing data read from said disk storage device, in which recognized errors are corrected before the data are forwarded to said data processing system; said buffer memory having a storage disk capacity corresponding to the maximum quantity of data that can be read from said disk storage device by a single read instruction; successively transferring the data blocks read during a single read instruction into said buffer, without interruption, despite data errors that may be recognized; calculating check characters in response to the data written into said buffer, while said data is being written; comparing the calculated check characters with check characters transmitted from said disk storage device, and in response to a noncomparison of such check characters, forming an error syndrome corresponding to the recognized error; and intermediately storing said calculated error syndrome at a storage location allocated to the data containing the recognized error; and correcting the data within said buffer memory in response to said calculated error syndrome before said data is read out from said buffer memory to said data processing system.
Claim 2
Independent Claim
234 words
A method for controlling error correction within a data transmission controller, said transmission controller controlling the transmission of data from a disk storage device to a data processing system, said data being recorded in said disk storage device in a plurality of blocks with check characters, said method comprising the steps of: providing a buffer memory for intermediately storing data read from said disk storage device, in which recognized errors are corrected before the data are forwarded to said data processing system; said buffer memory having a storage disk capacity corresponding to the maximum quantity of data that can be read from said disk storage device by a single read instruction; successively transferring the data blocks read during a single read instruction into said buffer, without interruption, despite data errors that may be recognized; calculating check characters in response to the data written into said buffer, while said data is being written; comparing the calculated check characters with check characters transmitted from said disk storage device, and in response to a noncomparison of such check characters, forming an error syndrome corresponding to the recognized error; and intermediately storing said calculated error syndrome at a storage location allocated to the data containing the recognized error; and correcting the data within said buffer memory in response to said calculated error syndrome before said data is read out from said buffer memory to said data processing system.
Claim 3
Dependent Claim
46 words
The method according to claim 1, including the step of calculating correction quantities for the correction of said data stored in said buffer only after all of the data read from said disk storage device during a single read instruction has been stored in said buffer.
Claim 4
Dependent Claim
22 words
The method according to claim 2, including the step of calculating said error correction quantities, in response to said stored error syndromes.
Claim 5
Independent Claim
35 words
The method according to either of claims 2 or 3, including the step of correcting the erroneous data stored in said buffer memory, immediately after the calculation of the correction quantities applicable to such data.
Claim 6
Dependent Claim
49 words
The method according to claim 3, including the step of providing means for reading and writing said buffer memory in parallel units of said data, and transferring said data in parallel between said buffer memory and a correction device, whereby erroneous data stored in said buffer memory is corrected.
Claim 7
Independent Claim
66 words
A method according to any of the claims 1 through 3, including the step of correcting a subset of the data stored in said buffer, after all of the data read during a single read instruction is stored therein, and forwarding a corrected subset as soon as it has been corrected, before the remainder of the data is stored in said buffer memory has been corrected.
Claim 8
Independent Claim
183 words
The method according to any of the claims 1 through 3, including the step of providing transfer units between said disk storage device and said buffer and between said buffer and said data processing system, an executive sequencer comprising a microprocessor with a main memory for controlling the transfer between said disk storage device and said buffer memory, and the transfer between said buffer memory and said data processing system, providing a data bus for interconnecting the data path from said disk storage device to said buffer memory and from said buffer memory to said data processing system, providing a correction device interconnected with said data bus whereby the data is transferred between said buffer memory and said correction device for the purpose of correcting data stored in said buffer which has recognized errors, and providing a control bus, separate from said data bus, for interconnecting said executive sequencer with said buffer, said correction unit, and said transfer units, and monitoring the operation of said transfer devices, said buffer memory, and said correction unit with said microprocessor without interferring with said data bus.
Claim 9
Dependent Claim
40 words
The method according to claim 7, including the step of storing, within said correction unit, error syndromes corresponding to recognized errors, together with an allocation identifier identifying the data to which said error syndrome is allocated within said correction unit.
Claim 10
Dependent Claim
85 words
The method according to claim 7, including the step of providing a transfer register for intermediately storing said calculated error syndrome together with allocation identifiers identifying the data to which said error syndromes are allocated, transferring said error syndromes and said identifiers to the main memory of said executive sequencer for intermediate storage via said control bus, and transferring said error syndromes and said identifiers from said executive sequencer to said correction unit for the correction of errors in the data stored in said buffer.
Claim 11
Dependent Claim
181 words
Apparatus for controlling error correction within a data processing controller for controlling data read from a disk storage device to a data processing system, comprising, in combination: a buffer memory connected to receive and store data read from said disk storage device, said buffer memory having a storage capacity corresponding to the maximum quantity of data that can be read from said disk storage device with a single read instruction, protection and correction means connected to receive data from said disk storage device for generating protection characters. an error syndrome generator, for generating error syndromes corresponding to said protection characters and to in the data stored in said buffer, a syndrome buffer memory connected to said error syndrome generator for intermediately storing said error syndromes; a vector generator connected to said syndrome buffer memory for generating correction quantities corresponding to said error syndromes, and means for generating timed control signals for controlling said syndrome buffer memory and said vector generator, for intermediately storing said error syndromes and correcting errors in data stored in said buffer memory in accordance with said syndromes.
Claim 12
Dependent Claim
181 words
Apparatus for controlling error correction within a data processing controller for controlling data read from a disk storage device to a data processing system, comprising, in combination: a buffer memory connected to receive and store data read from said disk storage device, said buffer memory having a storage capacity corresponding to the maximum quantity of data that can be read from said disk storage device with a single read instruction, protection and correction means connected to receive data from said disk storage device for generating protection characters. an error syndrome generator, for generating error syndromes corresponding to said protection characters and to in the data stored in said buffer, a syndrome buffer memory connected to said error syndrome generator for intermediately storing said error syndromes; a vector generator connected to said syndrome buffer memory for generating correction quantities corresponding to said error syndromes, and means for generating timed control signals for controlling said syndrome buffer memory and said vector generator, for intermediately storing said error syndromes and correcting errors in data stored in said buffer memory in accordance with said syndromes.
Claim 13
Dependent Claim
31 words
Apparatus according to claim 10, wherein said buffer memory has separate read and write ports, whereby different storage locations within said buffer memory may be simultaneously read from and written to.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-29 | 1993-07-31 | 1994-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-29 | 1997-07-31 | 1998-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-29 | 2001-07-31 | 2002-01-30 | $7700.00 | Window Closed / Lapsed |