Wide band amplifier with current mirror feedback to bias circuit

Claim 3

The method of claim 1 wherein step (a) includes sensing the emitter current and producing the first current by means of a first current mirror circuit.

Claim 4

The method of claim 2 including compensating the bias circut's response to the third current by coupling a capacitor to the first conductor, the wideband amplifier, the bias circuit, the first field effect transistor, the first current mirror circuit, and the capacitor all being included on a monolithic integrated circuit chip.

Claim 5

The method of claim 3 wherein step (a) includes sensing an emitter current of a third transistor in the output stage and producing a fifth current that is smaller by the first factor than the emitter current of the third transistor, summing the fifth current and the first current, and wherein step (b) includes splitting the sum of the fifth and first currents.

Claim 6

In a wideband amplifier including an input stage, an output stage, and a bias circuit, the improvement comprising in combination: (a) means for sensing an emitter current of a first transistor of the output stage and producing in response thereto a first current that is smaller by a first factor than the emitter current of the first transistor; (b) means for splitting a current having the magnitude of the first current into a second current and a third current which is smaller by a second factor than the first current; (c) means for conducting the third current out of a second transistor having its collector coupled by a first conductor to a gate electrode of a first field effect transistor, the first field effect transistor being a control transistor of the bias circuit; (d) means for supplying a fourth current to the first conductor by means of a constant current source circuit, the bias circuit adjusting a voltage on a base electrode of the first transistor to cause the third current to be equal to the fourth current.

Claim 7

In a wideband amplifier including an input stage, an output stage, and a bias circuit, the improvement comprising in combination: (a) means for sensing an emitter current of a first transistor of the output stage and producing in response thereto a first current that is smaller by a first factor than the emitter current of the first transistor; (b) means for splitting a current having the magnitude of the first current into a second current and a third current which is smaller by a second factor than the first current; (c) means for conducting the third current out of a second transistor having its collector coupled by a first conductor to a gate electrode of a first field effect transistor, the first field effect transistor being a control transistor of the bias circuit; (d) means for supplying a fourth current to the first conductor by means of a constant current source circuit, the bias circuit adjusting a voltage on a base electrode of the first transistor to cause the third current to be equal to the fourth current.

Claim 8

The improvement of claim 5 wherein the sensing and first current producing means includes a first current mirror circuit coupled in series with the emitter of the first transistor and producing the first current.

Claim 9

The improvement of claim 6 including a compensation capacitor coupled to the first conductor.

Claim 10

The improvement of claim 7 including means for sensing an emitter current of a third transistor of the output stage and producing a fifth current that is smaller by the first factor than the emitter current of the third transistor and means for summing the fifth current and the first current, the first current splitting means splitting the sum of the fifth and first currents.

Claim 13

The method of claim 9 including compensating the error signal by means of a compensation capacitor, the amplifier and the compensation capacitor being on a single integrated circuit chip.

Claim 14

The method of claim 10 wherein step (a) includes scaling the first mirrored current to a first fraction of the emitter current, wherein the certain percentage is a scaled second fraction of the first mirrored current.

Claim 17

The method of claim 12 wherein step (f) includes producing an error signal in response to the comparing and compensating the error signal by means of a compensation capacitor and step (g) includes applying a compensated error signal to an input transistor of a bias control circuit to adjust the DC bias current.

Claim 18

The method of claim 12 including applying the first mirrored current to a third current mirror circuit to reverse a direction of the first mirrored current before the summing of step (c).

Claim 19

The method of claim 14 including scaling down the first mirrored current by means of the third current mirror circuit before the summing of step (c).

Claim 20

In an amplifier, circuitry for controlling a DC bias current of an output stage of the amplifier by using feedback from the output stage to an input stage of the amplifier, this circuitry comprising in combination: (a) means for sensing an emitter current of a first transistor in the output stage with a first current mirror circuit to produce a first mirrored current; (b) means for producing a feedback current which is a certain percentage of the first mirrored current and causing the feedback current to flow through a second transistor; (c) means coupled to the second transistor for comparing the feedback current to a reference current to generate an error signal; and (d) means for adjusting the DC bias current of the output stage in response to the error signal to cause the feedback current to equal the reference current.

Claim 21

In an amplifier, circuitry for controlling a DC bias current of an output stage of the amplifier by using feedback from the output stage to an input stage of the amplifier, this circuitry comprising in combination: (a) means for sensing an emitter current of a first transistor in the output stage with a first current mirror circuit to produce a first mirrored current; (b) means for producing a feedback current which is a certain percentage of the first mirrored current and causing the feedback current to flow through a second transistor; (c) means coupled to the second transistor for comparing the feedback current to a reference current to generate an error signal; and (d) means for adjusting the DC bias current of the output stage in response to the error signal to cause the feedback current to equal the reference current.

Claim 22

The circuitry of claim 16 including a compensation capacitor connected to receive the error signal, the amplifier and the compensation capacitor being on a single integrated circuit chip.

Claim 23

The circuitry of claim 17 wherein the first mirrored current is a first fraction of the emitter current of the first transistor, and the certain percentage is a scaled down second fraction of the first mirrored current.

Claim 24

In an amplifier, circuitry for controlling a DC bias current of an output stage of an amplifier by using feedback from the output stage to an input stage, the circuitry comprising in combination: (a) first sensing means for sensing a first emitter current in a first transistor in the output stage by means of a first current mirror circuit to produce a first mirrored current, and second sensing means for sensing a second emitter current in a second transistor in the output stage by means of a second current mirror circuit to produce a second mirrored current; (b) a very high impedance current source supplying a reference current; (c) means for summing at least a certain fraction of the first mirrored current with the second mirrored current; (d) means for producing a feedback current which is a certain percentage of the sum of the first and second mirrored currents; (e) a third transistor and means for causing the feedback current to flow through the third transistor, the third transistor having an electrode with a very high impedance; (f) means coupled to the electrode for comparing the feedback current to the reference current to produce an error signal; (g) mean for adjusting the DC bias current of the output stage in response to the error signal so as to cause the feedback current to equal the reference current.

Claim 25

In an amplifier, circuitry for controlling a DC bias current of an output stage of an amplifier by using feedback from the output stage to an input stage, the circuitry comprising in combination: (a) first sensing means for sensing a first emitter current in a first transistor in the output stage by means of a first current mirror circuit to produce a first mirrored current, and second sensing means for sensing a second emitter current in a second transistor in the output stage by means of a second current mirror circuit to produce a second mirrored current; (b) a very high impedance current source supplying a reference current; (c) means for summing at least a certain fraction of the first mirrored current with the second mirrored current; (d) means for producing a feedback current which is a certain percentage of the sum of the first and second mirrored currents; (e) a third transistor and means for causing the feedback current to flow through the third transistor, the third transistor having an electrode with a very high impedance; (f) means coupled to the electrode for comparing the feedback current to the reference current to produce an error signal; (g) mean for adjusting the DC bias current of the output stage in response to the error signal so as to cause the feedback current to equal the reference current.

Claim 26

The circuitry of claim 19 including a compensation capacitor and means for applying a compensated error signal to an input transistor of a bias control circuit to adjust the DC bias current.

Claim 27

The circuitry of claim 19 including a third current mirror circuit receiving the first mirrored current and coupled to the summing means to reverse a direction of the first mirrored current thereof before the summing.

Claim 28

The circuitry of claim 21 wherein the first transistor is a PNP transistor, the first current mirror circuit includes a PNP control transistor having a collector coupled to an emitter of the first transistor and a PNP output transistor, the second transistor is an NPN transistor, and the second current mirror circuit includes an NPN control transistor and an NPN output transistor, the summing means being coupled to a collector of the PNP output transistor and the collector of the NPN output transistor.

Claim 29

The circuitry of claim 22 wherein the third current mirror circuit includes an NPN control transistor having a collector coupled to the collector of the PNP output transistor and an NPN output transistor coupled to a collector of the NPN output transistor of the second current mirror circuit.

Claim 30

The circuitry of claim 23 wherein the feedback current producing means include first and second NPN transistors having a common base connection and emitters connected to the collector of the NPN output transistor of the third current mirror circuit, the third transistor being an NPN transistor, a collector of the second NPN transistor being coupled to an emitter of the third transistor, an emitter area of the second NPN transistor being a small fraction of an emitter area of the first NPN transistor.

Claim 31

The circuitry of claim 24 wherein the first mirrored current is a small fraction of the emitter current of the first transistor and the second mirror current is a small fraction of the emitter current of the second transistor.