Analog integrated filter circuit

Claim 2

An analog integrated filter comprising: capacitance multiplier means, including a capacitor (C), having a first and a second terminal, for providing an effective capacitance M f times that of the capacitor, and including a feedback impedance dependent upon an applied current; resistance means, coupled to the capacitance multiplier means, for providing resistance operative in conjunction with the effective capacitance to provide filtering; and, DC bias-controlled current supplying circuit, coupled to the capacitance multiplier means, for providing a DC bias-controlled current having a temperature dependence which substantially cancels the cumulative temperature dependence of the feedback impedance and the resistance means, so that the filter has a constant operating frequency response characteristic as the filter operates over a range of temperatures.

Claim 3

The filter according to claim 1, wherein said capacitance multiplier means having a first and second pair of Darlington transistors, wherein the output emitter electrode of the first pair is coupled to that of the second pair, the base electrode of the first pair is connected to said resistance means (R 1 ) and to the first terminal of the capacitor (C), the base electrode of the second pair is coupled to a second resistor (R 2 ) and to the collector electrodes of the second pair of Darlington transistors, such that the first and the second resistors are coupled to a common junction.

Claim 4

The filter according to claim 2, wherein said filter includes an input resistor (R s ) for applying the input signal to the Darlington pair of said capacitance multiplier through the common junction, wherein said DC bias-controlled current supplying circuit includes: a circuit including a first resistor (R B1 ) for supplying a reference current, I H , wherein the magnitude of the reference current is proportional to the temperature of the integrated filter and inversely proportional to the resistance of the first resistor, (R B1 ), a circuit which is coupled to the reference current supplying circuit for supplying a first-controlled bias current, I o the magnitude of which is proportional to the reference current, a circuit coupled to the first-controlled bias current circuit for supplying a second controlled bias current, the magnitude of which is proportional to the first-controlled bias current, a second resistor (R EX ) disposed externally to the integrated filter and coupleable to the reference current supplying circuit for draining the reference current therethrough from the reference current supplying circuit, thereby providing a voltage drop (V EX ) thereacross by the reference current, thereby the amplitude of the first-controlled bias current is related such that ##EQU12## and V.sub.T =KT/q where n is a characteristic number of the emitter-to-base function of the integrated circuit K is Boltzman's constant T is temperature in Kelvin q is charge in coulombs A is a semiconductor junction area scaling ratio whereby said filter provides a 3 db cutoff frequency, f c , ##EQU13## wherein f c is made to be directly related to the ratio ##EQU14## and thereby f c is made immune to the thermal drift of the individual resistors in the integrated filter, and insensitive to absolute value changes of the individual resistors in the integrated filter.

Claim 5

The filter according to claim 3, wherein the cutoff frequency, f c is changed to a different value by changing the resistance value of the second resistor R EX , whereby the filter is rendered programmable to provide different f c .

Claim 6

The filter according to claims 3 or 4, including a first grounded capacitance multiplier by grounding the second terminal of the capacitor of the multiplier, said first bias control current applied to the emitter electrodes of the two Darlington pairs as current sinks, and a second bias control current applied to the common junction, said second bias control current having an amplitude which is a predetermined portion of said first bias control, whereby the filter is rendered to operate as a low pass filter.

Claim 7

The filter according to claim 5, including the first grounded capacitance multiplier is coupled to receive an input signal and a subtractive circuit coupled to receive the input signal and the output of the first grounded multiplier and provide an output whereby the filter is rendered to operate as a high pass filter.

Claim 8

The filter according to claim 3, wherein the second terminal of said capacitance multiplier is coupled to receive an input signal and providing output at the common junction thereby forming a unidirectional capacitance multiplier.

Claim 9

The filter according to claim 7 having means for applying an input signal to the unidirectional capacitance multiplier and output circuit coupled to the common junction for providing an output of the filter whereby the filter is rendered to operate as a high pass filter.

Claim 10

The filter according to claim 3 connecting the second terminal of the capacitor to the collector electrode of the first Darlington pair and supplying the second bias control current to the junction of the capacitor and the collector electrode of the first Darlington pair, thereby forming a bidirectional multiplier.

Claim 11

The filter according to claim 7, including a first grounded capacitance multiplier by grounding the second terminal of the capacitor of the multiplier, said first bias control current applied to the emitter electrodes of the two Darlington pairs as current sinks, and a second bias control current applied to the common junction, said second bias control current having an amplitude which is a predetermined portion of said first bias control, whereby the filter is rendered to operate as a low pass filter, and a second capacitance multiplier arranged in the form of said unidirectional capacitance multiplier shunted across the first-grounded capacitance multiplier in a feedback mode, to provide a second-order low pass filter.