Frequency compensated high frequency amplifiers

Claim 2

A frequency compensated high frequency amplifier, including in combination: a first gain stage; a second gain stage having a first high impedance node coupled to said first gain stage, a second high impedance node, non-inverting amplifier means electrically connected between said first and second high impedance nodes, a third high impedance node, inverting amplifier means having an input terminal coupled to said second high impedance node for receiving signals therefrom, said inverting amplifier means havig an output terminal connected to said third high impedance node for applying such signals to said third high impedance node after inverting such signals, the impedances at said first, second and third high impedance nodes being a function of frequency and said second high impedance node having a lower impedance at a given frequency than the impedances at said first and third high impedance nodes; first frequency compensating capacitive means coupled between said first and third high impedance nodes; and second frequency compensating capacitive means coupled between said third and second high impedance nodes.

Claim 3

The amplifier circuit of claim 1 wherein said non-inverting amplifier means includes: a bipolar transistor having emitter, base and collector electrodes, said base electrode being directly connected to said first high impedance node and said emitter electrode being directly connected to said second high impedance node; and current supply means connected to said collector electrode.

Claim 4

The amplifier circuit of claim 2 further including current sink means electrically connected to said emitter electrode.

Claim 5

The amplifier circuit of claim 1 wherein said inverting amplifier means includes: a bipolar transistor having an emitter, base and collector electrodes, said base electrode being connected to said second high impedance node; and current supply means connected to said collector electrode.

Claim 6

The amplifier circuit of claim 1 further including: circuit means connected in a series circuit with said second frequency compensation capacitive means; said series circuit being coupled between said third high impedance node and said second high impedance node, said circuit means including a pair of complementary output transistors which provide the output signal for the amplifier.

Claim 7

The amplifier circuit of claim 5 further including bias means for said complementary output transistors.

Claim 8

A second gain stage for a frequency compensated high frequency amplifier having a first gain stage, the high frequency amplifier being suitable for being manufactured in monolithic integrated circuit form, the second gain stage including in combination: a first high impedance node coupled to the first gain stage; a second high impedance node; a non-inverting amplifier having a first transistor with an emitter electrode, a collector electrode and a base electrode, said base electrode of said first transistor being connected to said first high impedance node, said emitter electrode of said first transistor being coupled to said second high impedance node; a first current supply connected to said collector electrode of said first transistor; current sink means connected to said emitter electrode of said first transistor; a third high impedance node; an inverting amplifier having a second transistor with an emitter electrode, a base electrode and a collector electrode, said base electrode of said second transistor being connected to said second high impedance node for receiving signals therefrom and said collector electrode of said second transistor being connected to said third high impedance node, said second transistor thereby being adapted to apply inverted signals to said third high impedance node; a second current supply connected to said third high impedance node; a pair of complementary output transistors being electrically coupled between said third high impedance node and an output terminal for the high frequency amplifier; the impedances at said first, second and third high impedance nodes being a function of frequency and said second high impedance node having a lower impedance at a given frequency than the impedances of said first and third high impedance nodes; first frequency compensating capacitive means coupled between said first and third nodes; and second frequency compensating capacitive means coupled between said output terminal of the high frequency amplifier and said second high impedance node.

Claim 9

A second gain stage for a frequency compensated high frequency amplifier having a first gain stage, the high frequency amplifier being suitable for being manufactured in monolithic integrated circuit form, the second gain stage including in combination: a first high impedance node coupled to the first gain stage; a second high impedance node; a non-inverting amplifier having a first transistor with an emitter electrode, a collector electrode and a base electrode, said base electrode of said first transistor being connected to said first high impedance node, said emitter electrode of said first transistor being coupled to said second high impedance node; a first current supply connected to said collector electrode of said first transistor; current sink means connected to said emitter electrode of said first transistor; a third high impedance node; an inverting amplifier having a second transistor with an emitter electrode, a base electrode and a collector electrode, said base electrode of said second transistor being connected to said second high impedance node for receiving signals therefrom and said collector electrode of said second transistor being connected to said third high impedance node, said second transistor thereby being adapted to apply inverted signals to said third high impedance node; a second current supply connected to said third high impedance node; a pair of complementary output transistors being electrically coupled between said third high impedance node and an output terminal for the high frequency amplifier; the impedances at said first, second and third high impedance nodes being a function of frequency and said second high impedance node having a lower impedance at a given frequency than the impedances of said first and third high impedance nodes; first frequency compensating capacitive means coupled between said first and third nodes; and second frequency compensating capacitive means coupled between said output terminal of the high frequency amplifier and said second high impedance node.

Claim 10

The circuit of claim 7 further including in combination: bias circuit means coupled with said pair of complementary transistors; and a third current supply connected to said bias circuit means.