Patent US4894561A successfully refreshed from Google Patents.
US4894561A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS inverter having temperature and supply voltage variation compensation
Assignee: Toshiba Corp
•
Filing: 1988-10-13
•
Granted: 1990-01-16
•
Expires: 2008-10-13
Abstract
Abstract A semiconductor integrated circuit comprises a pair of P-channel and N-channel MOS output transistors connected in series between a power source voltage node and a ground node, a first logic circuit for controlling a gate potential of the P-channel MOS output transistor, a first current control circuit for controlling a current flowing into a ground potential path of the first logic circuit, a second logic circuit for controlling a gate potential of the N-channel MOS output transistor, a second current control circuit for controlling a current flowing into a power source potential path of the second logic circuit, and the first and second current control circuits having a current-temperature characteristic and a current-power source voltage characteristic which are inversely proportional to those of the MOS output transistors. With such an arrangement, the power source voltage dependency and the temperature dependency of the MOS output transistors are cancelled out by the control currents of the first and second current control circuits. Thus, the output voltage of the output circuit depends little on the change of the power source voltage and the operating temperature.
Inventors
- 👤 Kazutaka Nogami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:45
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00369; H03K19/00384; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242; G05F3/245
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
127 words
A semiconductor integrated circuit comprising: a pair of P-channel and N-channel MOS output transistors connected in series between a power source voltage node and a ground node; a first logic circuit for controlling a gate potential of said P-channel MOS output transistor; a first current control circuit for controlling a current flowing into a ground potential path of said first logic circuit; a second logic circuit for controlling a gate potential of said N-channel MOS output transistor; a second current control circuit for controlling a current flowing into a power source potential path of said second logic circuit; and said first and second current control circuits having a current-temperature characteristic and a current-power source voltage characteristic which are inversely proportional to those of said MOS output transistors.
Claim 2
Dependent Claim
127 words
A semiconductor integrated circuit comprising: a pair of P-channel and N-channel MOS output transistors connected in series between a power source voltage node and a ground node; a first logic circuit for controlling a gate potential of said P-channel MOS output transistor; a first current control circuit for controlling a current flowing into a ground potential path of said first logic circuit; a second logic circuit for controlling a gate potential of said N-channel MOS output transistor; a second current control circuit for controlling a current flowing into a power source potential path of said second logic circuit; and said first and second current control circuits having a current-temperature characteristic and a current-power source voltage characteristic which are inversely proportional to those of said MOS output transistors.
Claim 3
Dependent Claim
85 words
A semiconductor integrated circuit according to claim 1, in which, in said second current control circuit, the output voltage of a first differential amplifier comprising an N-channel MOS transistor and a resistive element coupled in a differential manner is applied to the gate of a current controlling P-channel MOS transistor, and the output voltage of a second differential amplifier comprising a P-channel MOS transistor and a resistive element coupled in a differential manner is applied to the gate of a current controlling N-channel MOS transistor.
Claim 4
Dependent Claim
29 words
A semiconductor integrated circuit according to claim 2, in which two stages of said first differential amplifiers are used, and two stages of said second differential amplifiers are used.
Claim 5
Dependent Claim
26 words
A semiconductor integrated circuit according to claim 2, in which said resistive elements are made of the same material as the gates of said MOS transistors.
Claim 6
Dependent Claim
86 words
A semiconductor integrated circuit according to claim 1, further comprising a third current control circuit for controlling a current flowing through the power source potential path of said first logic circuit, and a fourth current control circuit for controlling a current flowing through the ground potential path of said second logic circuit, and said third current control circuit has substantially the circuit arrangement as said second current control circuit, and said fourth current control circuit has substantially the circuit arrangement as said first current control circuit.
Claim 7
Dependent Claim
86 words
A semiconductor integrated circuit according to claim 2, further comprising a third current control circuit for controlling a current flowing through the power source potential path of said first logic circuit, and a fourth current control circuit for controlling a current flowing through the ground potential path of said second logic circuit, and said third current control circuit has substantially the circuit arrangement as said second current control circuit, and said fourth current control circuit has substantially the circuit arrangement as said first current control circuit.
Claim 8
Dependent Claim
86 words
A semiconductor integrated circuit according to claim 4, further comprising a third current control circuit for controlling a current flowing through the power source potential path of said first logic circuit, and a fourth current control circuit for controlling a current flowing through the ground potential path of said second logic circuit, and said third current control circuit has substantially the circuit arrangement as said second current control circuit, and said fourth current control circuit has substantially the circuit arrangement as said first current control circuit.
References Cited (Backward Citations)
US4473762A
Cited
US4593203A
Cited
US4645948A
Cited
US4785203A
Cited
US4736123A
Cited
US4827159A
Cited
US4749882A
Cited
US4760292A
Cited
US4792704A
Cited
US4797579A
Cited
US4825101A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-15 | 1993-07-17 | 1994-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-15 | 1997-07-17 | 1998-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-15 | 2001-07-17 | 2002-01-16 | $7700.00 | Window Closed / Lapsed |