Fully synchronized programmable counter with a near 50% duty cycle output signal

Claim 2

Apparatus for a fully synchronized, programmable frequency divider exhibiting a near 50% duty cycle output signal which is independent of the divisor therein, whether even or odd, the apparatus comprising: (a) counting means for counting to a selected integer so that division of an applied input signal frequency is accomplished by a divisor equalling the selected integer; (b) data loading means, responsive to a command signal, for storing and then automatically loading a new or same integer into said counting means to provide the selected integer as a present divisor for said counting means; (c) half-period detecting means, coupled to the counting means and the data loading means, for detecting an integer-approximated half-period of the input signal by compairing when the count within the counting means equals the state INTEGER (N/2) and outputting an indicating thereof; and (d) synchronizing means, coupled to the counting means and the data loading means, and responsive to the indication outputted from the half-period detecting means, for synchronizing the data loading of said counting means, and for synchronizing the output signal with respect to the input signal, thereby providing a near 50% duty cycle output signal which is independent of the present divisor therein.

Claim 3

The apparatus according to claim 1, wherein said counting means comprises a plurality of cascaded flip-flops, a NOR gate, and an OR gate, so as to provide the divisor given by the selected integer.

Claim 4

The apparatus according to claim 1, wherein said counting means includes a plurality of cascaded flip-flops configured and arranged to count downward in order to effect the present divisor.

Claim 5

The apparatus according to claim 1, wherein said data loading means comprises a plurality of latches.

Claim 6

The apparatus according to claim 1, wherein said half-period detecting means comprises a plurality of EXCLUSIVE NOR gates and an AND gate configured to detect a count which is approximately one-half of said selected integer utilized for the divisor.

Claim 7

The apparatus according to claim 1, wherein said half-period detecting means comprises a plurality of EXCLUSIVE NOR gates and an AND gate configured to detect a count which is exactly one-half of said selected integer utilized for the divisor when said integer is even, and to detect a count which is approximately one-half of said selected integer utilized for the divisor when said integer is odd.

Claim 8

The apparatus according to claim 1, wherein said synchronizing means comprises a first resettable flip-flop and a second flip-flop, said first flip-flop for automatically loading data into said counting means, and both of said first and said second flip-flops for synchronizing the output signal with respect to the input signal.

Claim 9

Apparatus for a fully synchronized, programmable frequency divider exhibiting an output signal which has a duty cycle virtually equal to 50% and independent of the divisor therein, whether even or odd, the apparatus comprising: (a) counting means for counting to a selected integer so that division of an applied input signal frequency is accomplished by a divisor equalling the selected integer; (b) data loading means, responsive to a command signal, for storing and then automatically loading a new or same integer into said counting means to provide the selected integer as a present divisor for said counting means; (c) half-clock period detecting means, coupled to the counting means and the data loading means as well as to the input signal, for detecting only when said selected integer is odd, a half clock period of the input signal and providing an indication thereof; (d) half-period detecting means, coupled to the counting means, the data loading means, and the half-clock period detecting means, for detecting a half-period of the input signal by compairing when the count within the counting means equals the state (N/2) and outputting an exact indication thereof; and (e) synchronizing means, coupled to, the counting means, the data loading means the half-clock period detecting means and responsive to the indication outputted from the half-period detecting means, for synchronizing the data loading of said counting means and for synchronizing the output signal with respect to the input signal, said output signal routed through included output logic means depending on whether said divisor is even or odd, thereby providing an output signal having a duty cycle, virtually equal to 50%, which is independent of the present divisor therein.

Claim 10

Apparatus for a fully synchronized, programmable frequency divider exhibiting an output signal which has a duty cycle virtually equal to 50% and independent of the divisor therein, whether even or odd, the apparatus comprising: (a) counting means for counting to a selected integer so that division of an applied input signal frequency is accomplished by a divisor equalling the selected integer; (b) data loading means, responsive to a command signal, for storing and then automatically loading a new or same integer into said counting means to provide the selected integer as a present divisor for said counting means; (c) half-clock period detecting means, coupled to the counting means and the data loading means as well as to the input signal, for detecting only when said selected integer is odd, a half clock period of the input signal and providing an indication thereof; (d) half-period detecting means, coupled to the counting means, the data loading means, and the half-clock period detecting means, for detecting a half-period of the input signal by compairing when the count within the counting means equals the state (N/2) and outputting an exact indication thereof; and (e) synchronizing means, coupled to, the counting means, the data loading means the half-clock period detecting means and responsive to the indication outputted from the half-period detecting means, for synchronizing the data loading of said counting means and for synchronizing the output signal with respect to the input signal, said output signal routed through included output logic means depending on whether said divisor is even or odd, thereby providing an output signal having a duty cycle, virtually equal to 50%, which is independent of the present divisor therein.

Claim 11

The apparatus according to claim 8, wherein said counting means comprises a plurality of cascaded flip-flops, a NOR gate, and an OR gate, so as to provide the divisor given by the selected integer.

Claim 12

The apparatus according to claim 8, wherein said counting means includes a plurality of cascaded flip-flops configured and arranged to count downward in order to effect the present divisor.

Claim 13

The apparatus according to claim 8, wherein said data loading means comprises a plurality of latches.

Claim 14

The apparatus according to claim 8, wherein said half-period detecting means comprises a plurality of exclusive NOR gates and an AND gate configured to detect a count which is exactly one-half of said selected integer utilized for the divisor when said integer is even, and to detect a count which is exactly one-half of said selected integer utilized for the divisor when said integer is odd.

Claim 15

The apparatus according to claim 8, wherein said half-clock period detecting means comprises an inverter, an AND gate, and an OR gate, coupled to (a), (b), (c) above, as well as to the input signal.

Claim 16

The apparatus according to claim 8, wherein said synchronizing means comprises: first and second synchronization flip-flops, said first flip-flop outputting a synchronized control signal to said second flip-flop which is clocked by the input signal; and said output logic circuit comprises: a third flip-flop and an array of logic gates which synchronize the data loading into said counter, and which permit synchronization of the output signal for even integer divisors by utilizing said second flip-flop, and for odd integer divisors by utilizing said third flip-flop.