Method and apparatus for decoding error correcting code

Claim 1

An error correcting code decoding apparatus comprising: means for receiving a digital signal train V(X) added with an error correcting code on the basis of a generator polynominal G(X) formed by a first primitive polynominal G 1 (X) and a second primitive polynominal G 2 (X); first syndrome calculating means for dividing said received signal train V(X) by said first primitive polynominal G 1 (X) to obtain a syndrome S 1 (X), being the remainder term, said first primitive polynominal G 1 (X) being a polynominal of degree m (m: positive integer), said syndrome S 1 (X) being obtained by dividing said signal train V(X), including a single-bit error, by said first primitive polynominal G 1 (X) being in a cycle of 2 m -1; second syndrome calculating means for dividing said received signal train V(X) by said second primitive polynominal G 2 (X) to obtain an actual syndrome S 2 (X), being the remainder term, said second primitive polynominal G 2 (X) being a polynominal of said degree m, said actual syndrome S 2 (X) being obtained by dividing said signal train V(X), including said single-bit error, by said second primitive polynominal G 2 (X) being in a cycle of (2 m -1)/n (n: positive integer); error position calculating means for obtaining a single-bit error position l of said received signal train on the basis of said syndrome S 1 (X) obtained by said first syndrome calculating means; means for obtaining an assumed syndrome S 2 '(X) corresponding to said single-bit error position l calculated by said error position calculating means among values of said actual syndrome S 2 (X) corresponding to single-bit errors; means for comparing said actual syndrome S 2 (X) outputted from said second syndrome calculating means with said assumed syndrome S 2 '(X); and means for judging that said received signal train V(X) includes said single-bit error upon coincidence of said actual syndrome S 2 (X) with said assumed syndrome S 2 '(X) while judging that said received signal train V(X) includes a double-bit error or a multiple-bit error upon non-coincidence as the result of comparison by said comparing means.