US4751704A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for decoding BCH code
Assignee: Sony Corp
•
Filing: 1986-06-04
•
Granted: 1988-06-14
•
Expires: 2006-06-04
Abstract
Abstract Apparatus for decoding BCH code can correct double errors using a modification of the Chien search method. This decoding apparatus comprises circuits to form syndromes S1 and S3; a circuit to form S1 2 ; a circuit to form S1 3 ; a circuit to form (S1 3 +S3); and Chien search circuit, in which the error-location polynomial σ(x)=(S1x 2 +S1 2 x+S1 3 +S3) is solved, thereby correcting errors of two or less. With this apparatus, there is no need to perform a dividing process, and a high decoding processing speed can be realized without using any PLA or ROM.
Inventors
- 👤 Yuichi Kojima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 03:54
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/13; H03M13/15; H03M13/151
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
100 words
An apparatus for decoding BCH code comprising: first and second circuits to form syndromes S1 and S3, respectively, from a receiving sequence; a third circuit connected with said first circuit to form S1 2 from the syndrome S1; a fourth circuit connected with said first and third circuits to form S1 3 from the syndrome S1; a fifth circuit connected to form (S1 3 +S3); and a Chien search circuit connected with said first, third and fifth circuits to receive said S1, S1 2 , and (S1 3 +S3), and to solve the error-location polynomial (σ(x)=S1 x.sup.2 +S1.sup.2 x+S1.sup.3 +S3)
Claim 2
Independent Claim
100 words
An apparatus for decoding BCH code comprising: first and second circuits to form syndromes S1 and S3, respectively, from a receiving sequence; a third circuit connected with said first circuit to form S1 2 from the syndrome S1; a fourth circuit connected with said first and third circuits to form S1 3 from the syndrome S1; a fifth circuit connected to form (S1 3 +S3); and a Chien search circuit connected with said first, third and fifth circuits to receive said S1, S1 2 , and (S1 3 +S3), and to solve the error-location polynomial (σ(x)=S1 x.sup.2 +S1.sup.2 x+S1.sup.3 +S3)
Claim 3
Dependent Claim
11 words
thereby correcting errors of two or less in said receiving sequence.
Claim 4
Dependent Claim
11 words
thereby correcting errors of two or less in said receiving sequence.
Claim 5
Dependent Claim
23 words
An apparatus for decording BCH code according to claim 1, wherein said fourth circuit to form S1 3 multiplies S1 2 with S1.
Claim 6
Dependent Claim
53 words
An apparatus for decoding BCH code according to claim 1, including a zero detecting circuit which is supplied with said syndromes S1 and S3, and a gating circuit connected to said zero detecting circuit to inhibit an output of said Chien search circuit when both of said syndromes S1 and S3 are 0.
Claim 7
Independent Claim
83 words
A method for decoding BCH code, including the steps of first forming the syndrome S1 and S3 from a receiving sequence, then forming S1 2 and S1 3 from S1 and S1 2 respectively, combining said syndromes to form (S1 3 +S3), and using a Chien search circuit to produce an output signal corresponding to σ(x)=S1 x 2 +S1 2 x+S1 3 +S3, and inverting bits in said receiving sequence in accordance with said output signal, thereby correcting errors in said receiving sequence.
Claim 8
Independent Claim
83 words
A method for decoding BCH code, including the steps of first forming the syndrome S1 and S3 from a receiving sequence, then forming S1 2 and S1 3 from S1 and S1 2 respectively, combining said syndromes to form (S1 3 +S3), and using a Chien search circuit to produce an output signal corresponding to σ(x)=S1 x 2 +S1 2 x+S1 3 +S3, and inverting bits in said receiving sequence in accordance with said output signal, thereby correcting errors in said receiving sequence.
References Cited (Backward Citations)
US3278729A
Cited
US3418629A
Cited
US3781791A
Cited
US4162480A
Cited
US4360916A
Cited
US4494234A
Cited
US4642808A
Cited
US4584686A
Cited
US4649541A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-14 | 1991-12-14 | 1992-06-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-14 | 1995-12-14 | 1996-06-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-14 | 1999-12-14 | 2000-06-14 | $7700.00 | Window Closed / Lapsed |