US3781791A
Expired / Lapsed
US
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Method and apparatus for decoding bch codes
Assignee: AT&T Inc
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Filing: 1971-12-13
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Granted: 1973-12-25
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Expires: 1991-12-13
Abstract
Abstract Apparatus is disclosed for performing Berlekamp''s algorithm to effect the decoding of binary BCH codes. In particular, in accordance with the present invention, Berlekamp''s algorithm is restated such that two variables are advantageously combined and a simplified circuit disclosed for performing the iterations specified by the restated algorithm.
Inventors
- 👤 D Sullivan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:11
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/13; H03M13/15; H03M13/151
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
102 words
In a system for decoding code words of a t-error-correcting binary BCH code including means for generating the power sum symmetric functions, S1, S2...S2t, of said code words, a field processor responsive to said power sum symmetric function generating means for generating signals corresponding to the terms of the error-locator polynomial of said code words wherein said field processor comprises a. delta register means for successively generating signals corresponding to the function delta (2k 2) delta (2k) + Delta 1(2k)z Tau (2k), b. Tau register means responsive to signals from said delta register means for successively generating signals corresponding to the function,
Claim 2
Dependent Claim
102 words
In a system for decoding code words of a t-error-correcting binary BCH code including means for generating the power sum symmetric functions, S1, S2...S2t, of said code words, a field processor responsive to said power sum symmetric function generating means for generating signals corresponding to the terms of the error-locator polynomial of said code words wherein said field processor comprises a. delta register means for successively generating signals corresponding to the function delta (2k 2) delta (2k) + Delta 1(2k)z Tau (2k), b. Tau register means responsive to signals from said delta register means for successively generating signals corresponding to the function,
Claim 3
Dependent Claim
18 words
logic circuit means interconnecting said shift register stages, said logic circuit means including two position switch means, and
Claim 4
Dependent Claim
18 words
logic circuit means interconnecting said shift register stages, said logic circuit means including two position switch means, and
Claim 5
Dependent Claim
41 words
A system as in claim 1 further including Chien search means responsive to the signals from said field processor for generating signals corresponding to the roots of said error-locator polynomial and for correcting, at most, t errors in said code words.
Claim 6
Dependent Claim
69 words
means responsive to the contents of said shift register stages and to signals representative of Delta 1(2k) for generating control signals for controlling said switch means to be in a predetermined one of said two positions, said sequential circuit thereby comprising a binary counter when said two-position switch is in one of said two positions and comprising a mod2t complementing circuit when in the other of said two positions.
Claim 7
Dependent Claim
69 words
means responsive to the contents of said shift register stages and to signals representative of Delta 1(2k) for generating control signals for controlling said switch means to be in a predetermined one of said two positions, said sequential circuit thereby comprising a binary counter when said two-position switch is in one of said two positions and comprising a mod2t complementing circuit when in the other of said two positions.
Claim 8
Dependent Claim
37 words
Apparatus as in claim 2 wherein said field processor further includes means responsive to said Chien search means for signifying that the number of errors in said data stream exceeds the correcting capability, t, of said code.
Claim 9
Dependent Claim
45 words
Apparatus as in claim 3 wherein said delta register means comprises means for successively registering the values of delta (2k 2), said delta (2k 2) registering means including a plurality of stages designated z,z2,z3,..., for registering the coefficients of z,z2,z3,..., respectively, of delta (2k 2).
Claim 10
Dependent Claim
44 words
Apparatus as in claim 4 wherein said Tau register means comprises means for registering successive values of Tau (2k 2), said Tau (2k 2) registering means including a plurality of stages designated z,z2,z3,..., for registering the coefficients of z,z2,z3,..., respectively, of Tau (2k 2).
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-24 | 1977-06-25 | 1977-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-24 | 1981-06-25 | 1981-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-24 | 1985-06-25 | 1985-12-25 | $7700.00 | Window Closed / Lapsed |