Method and apparatus for reducing aliasing in signal processing

Claim 2

An alias reducing signal processing apparatus comprising: jittered pulse means, operative to provide a sequence of jittered pulses, each pulse occurring during one of a sequence of time intervals of duration T at a time determined by a sequential one of a set of independent random numbers having a uniform probability density in a region bounded by zero and T; and processing means, in electrical communication with the jittered pulse means, operative to perform a signal processing operation in response to the jittered pulses.

Claim 3

Apparatus according to claim 1 wherein the random numbers are indicated by a random signal provided by a random signal generator, the generator comprising: a noise source, operative to provide a noise signal having a randomly varying value; a reference source, operative to provide a reference signal; reference signal correction means, having a first input in electrical communication with the noise source and a second input in electrical communication with the reference source, operative to generate a correction signal if the absolute value of the difference between the noise signal and the reference signal exceeds a bracket amount, the correction signal tending to change the value of the reference signal so as to reduce the absolute value of said difference; and comparator means, in electrical communication with the noise source and the reference source, operative to provide the random signal by comparing the value of the reference signal with the value of the noise signal.

Claim 4

Apparatus according to claim 1 wherein the jittered pulse means comprises digital processing means.

Claim 5

Apparatus according to claim 1 wherein the processing means comprises sampling means for sampling an externally provided input signal, operative to provide an output signal indicative of the value of the input signal when a jittered pulse is provided.

Claim 6

Apparatus according to claim 4 and further comprising logic means, electrically connected to the processing means, for providing a signal indicative of the time at which the jittered pulse is provided.

Claim 7

Apparatus according to claim 1 and further comprising a clock source, operative to provide a sequence of clock pulses having a period of duration T to define the sequence of time intervals.

Claim 8

Apparatus according to claim 6 wherein the jittered pulse means comprises delay means, in electrical communication with the clock source, operative to provide the jittered pulses by delaying sequential ones of the clock pulses for sequential ones of a set of time intervals determined by the random numbers.

Claim 9

Apparatus according to claim 7 wherein the delay means comprises: a random signal selector, in electrical communication with the clock source, operative to generate a random signal indicative of the random numbers and responsive to a clock pulse to provide a selected signal having a value determined by the random signal; a ramp source, in electrical communication with the clock source, responsive to a clock pulse to provide a ramp signal which begins at an initial value and increases at a constant rate; and comparator means, in electrical communication with the ramp source and the random signal selector, operative to provide a jittered pulse when the value of the ramp signal becomes equal to the value of the selected signal.

Claim 10

Apparatus according to claim 7 wherein the delay means comprises: a random signal selector, in electrical communication with the clock source, operative to generate a random signal indicative of the random numbers and responsive to a clock pulse to provide a selected signal having a value determined by the random signal; a ramp source, in electrical communication with the clock source and the random signal selector, responsive to a clock pulse to provide a ramp signal which begins at an initial value and increases at a rate determined by the value of the selected signal; and comparator means, in electrical communication with the ramp source, operative to provide a jittered pulse when the value of the ramp signal becomes equal to a predetermined value.

Claim 11

Apparatus according to claim 1 wherein the processing means comprises synthesis means, operative to synthesize an output signal having a desired frequency as specified by an externally provided control signal.

Claim 12

Apparatus according to claim 10 wherein the synthesis means comprises an accumulator operative to provide a carry pulse responsive to accumulation of a predetermined number of said jittered pulses.

Claim 13

Apparatus according to claim 10 wherein the synthesis means comprises a fractional divider means for counting said jittered pulses operative to provide a carry pulse responsive to a predetermined number of said jittered pulses.

Claim 14

Apparatus according to claim 10 and further comprising phase interpolator means.

Claim 15

Apparatus according to claim 10 and further comprising sine wave generation means.

Claim 16

An aliasing reducing frequency synthesizer for synthesizing an output signal having a desired frequency as specified by an externally provided control signal, the synthesizer comprising: a clock source, operative to provide a sequence of clock pulses having a period of duration T; synthesis means, in electrical communication with the clock source, responsive to the clock pulses and to the control signal to synthesize a sequence of carry pulses; and delay means, in electrical communication with the synthesis means, responsive to the carry pulses to provide an output signal having the desired frequency by delaying sequential ones of the carry pulses for sequential ones of a set of time intervals determined by a set of independent random numbers having a uniform probability density in a region bounded by zero and T.

Claim 17

An aliasing reducing frequency synthesizer for synthesizing an output signal having a desired frequency as specified by an externally provided control signal, the synthesizer comprising: a clock source, operative to provide a sequence of clock pulses having a period of duration T; synthesis means, in electrical communication with the clock source, responsive to the clock pulses and to the control signal to synthesize a sequence of carry pulses; and delay means, in electrical communication with the synthesis means, responsive to the carry pulses to provide an output signal having the desired frequency by delaying sequential ones of the carry pulses for sequential ones of a set of time intervals determined by a set of independent random numbers having a uniform probability density in a region bounded by zero and T.

Claim 18

A synthesizer according to claim 15 wherein the randon numbers are indicated by a random signal provided by a random signal generator, the generator comprising: a noise source, operative to provide a noise signal having a randomly varying value; a reference source, operative to provide a reference signal; reference signal correction means, having a first input in electrical communication with the noise source and a second input in electrical communication with the reference source, operative to generate a correction signal if the absolute value of the difference between the noise signal and the reference signal exceeds a bracket amount, the correction signal tending to change the value of the reference signal so as to reduce the absolute value of said difference; and comparator means, in electrical communication with the noise source and the reference source, operative to provide the random signal by comparing the value of the reference signal with the value of the noise signal.

Claim 19

A synthesizer according to claim 15 wherein the output signal comprises a sequence of output pulses and wherein the delay means comprises: a random signal selector, in electrical communication with the synthesis means, operative to generate a random signal indicative of the random numbers and responsive to a carry pulse to provide a selected signal having a value determined by the random signal; a ramp source, in electrical communication with the synthesis means, responsive to a carry pulse to provide a ramp signal which begins at an initial value and increases at a constant rate; and comparator means, in electrical communication with the ramp source and the random signal selector, operative to provide an output pulse when the value of the ramp signal becomes equal to the value of the selected signal.

Claim 20

A synthesizer according to claim 15 wherein the output signal comprises a sequence of output pulses and wherein the delay means comprises: a random signal selector, in electrical communication with the synthesis means, operative to generate a random signal indicative of the random numbers and responsive to a carry pulse to provide a selected signal having a value determined by the random signal; a ramp source, in electrical communication with the synthesis means and the random signal selector, responsive to a carry pulse to provide a ramp signal which begins at an initial value and increases at a rate determined by the value of the selected signal; and comparator means, in electrical communication with the ramp source, operative to provide an output pulse when the value of the ramp signal becomes equal to a predetermined value.

Claim 21

A synthesizer according to claim 15 wherein the synthesis means comprises an accumulator operative to provide a carry pulse responsive to accumulation of a predetermined number of said clock pulses.

Claim 22

A synthesizer according to claim 15 wherein the synthesis means comprises a fractional divider means for counting said clock pulses operative to provide a carry pulse responsive to a predetermined number of said clock pulses.

Claim 23

A synthesizer according to claim 15 wherein the synthesis means is operative to synthesize a phase signal indicative of any phase deviation between the carry pulses and the desired frequency, and further comprising phase interpolator means, in electrical communication with the delay means and the synthesis means, responsive to the phase signal and to the output signal from the delay means to provide a final output signal having the desired frequency.

Claim 24

A synthesizer according to claim 15 wherein the synthesis means is operative to synthesize a phase signal, and further comprising sine wave generation means, in electrical communication with the delay means and the synthesis means, responsive to the phase signal and to the output signal from the delay means to provide a final output signal having the desired frequency.

Claim 25

A phase-corrected aliasing reducing frequency synthesizer for synthesizing an output signal having a desired frequency as specified by an externally provided control signal, the synthesizer comprising: jittered pulse means, operative to provide a sequence of jittered pulses, each pulse occurring during one of a sequence of time intervals of duration T at a time determined by a sequential one of a set of independent random numbers having a uniform probability density in a region bounded by zero and T; phase correction means, in electrical communication with the jittered pulse means, operative to provide a phase corrected control signal by scaling the externally provided control signal according to the time intervals between sequential ones of the jittered pulses; and synthesis means, in electrical communication with the phase correction means and the jittered pulse means, responsive to the phase corrected control signal and the jittered pulses to provide an output signal having the desired frequency.

Claim 26

A phase-corrected aliasing reducing frequency synthesizer for synthesizing an output signal having a desired frequency as specified by an externally provided control signal, the synthesizer comprising: jittered pulse means, operative to provide a sequence of jittered pulses, each pulse occurring during one of a sequence of time intervals of duration T at a time determined by a sequential one of a set of independent random numbers having a uniform probability density in a region bounded by zero and T; phase correction means, in electrical communication with the jittered pulse means, operative to provide a phase corrected control signal by scaling the externally provided control signal according to the time intervals between sequential ones of the jittered pulses; and synthesis means, in electrical communication with the phase correction means and the jittered pulse means, responsive to the phase corrected control signal and the jittered pulses to provide an output signal having the desired frequency.

Claim 27

A synthesizer according to claim 23 wherein the random numbers are indicated by a random signal provided by a random signal generator, the generator comprising: a noise source, operative to provide a noise signal having a randomly varying value; a reference source, operative to provide a reference signal; reference signal correction means, having a first input in electrical communication with the noise source and a second input in electrical communication with the reference source, operative to generate a correction signal if the absolute value of the difference between the noise signal and the reference signal exceeds a bracket amount, the correction signal tending to change the value of the reference signal so as to reduce the absolute value of said difference; and comparator means, in electrical communication with the noise source and the reference source, operative to provide the random signal by comparing the value of the reference signal with the value of the noise signal.

Claim 28

A synthesizer according to claim 23 wherein the synthesis means comprises an accumulator operative to provide a carry pulse responsive to accumulation of a predetermined number of said jittered pulses.

Claim 29

A synthesizer according to claim 23 wherein the synthesis means comprises a fractional divider means for counting said jittered pulses operative to provide a carry pulse responsive to a predetermined number of said jittered pulses.

Claim 30

A synthesizer according to claim 23 and further comprising phase interpolator means.

Claim 31

A synthesizer according to claim 23 and further comprising sine wave generation means.

Claim 32

A synthesizer according to claim 23 wherein the jittered pulse means comprises digital processing means.

Claim 33

A synthesizer according to claim 29 wherein the phase correction means comprises: logic means, electrically connected to the digital processing means, operative to generate a phase correction signal proportional to the interval of time between successive jittered pulses; and scaling means, in electrical communication with the logic means, operative to provide the phase corrected control signal by scaling the externally provided control signal in proportion to the phase correction signal.

Claim 34

A synthesizer according to claim 23 and further comprising a clock source, operative to provide a sequence of clock pulses characterized by a period of duration T to define the sequence of time intervals.

Claim 35

A synthesizer according to claim 31 wherein the jittered pulse means comprises delay means, in electrical communication with the clock source, operative to provide the jittered pulses by delaying sequential ones of the clock pulses for sequential ones of a set of time intervals determined by the random numbers.

Claim 36

A synthesizer according to claim 32 wherein the delay means comprises: a random signal selector, in electrical communication with the clock source, operative to generate a random signal indicative of the random numbers and responsive to a clock pulse to provide a selected signal having a value determined by the random signal; a ramp source, in electrical communication with the clock source, responsive to a clock pulse to provide a ramp signal which begins at an initial value and increases at a constant rate; and comparator means, in electrical communication with the ramp source and the random signal selector, operative to provide a jittered pulse when the value of the ramp signal becomes equal to the value of the selected signal.

Claim 37

A synthesizer according to claim 33 wherein the phase correction means comprises: logic means, electrically connected to the random signal selector, responsive to the random signal to generate a phase correction signal proportional to the interval of time between successive jittered pulses; and scaling means, in electrical communication with the logic means, operative to provide the phase corrected control signal by scaling the externally provided control signal in proportion to the phase correction signal.

Claim 38

A synthesizer according to claim 32 wherein the delay means comprises: a random signal selector, in electrical communication with the clock source, operative to generate a random signal indicative of the random numbers and responsive to a clock pulse to provide a selected signal having a value determined by the random signal; a ramp source, in electrical communication with the clock source and the random signal selector, responsive to a clock pulse to provide a ramp signal which begins at an initial value and increases at a rate determined by the value of the selected signal; and comparator means, in electrical communication with the ramp source, operative to provide a jittered pulse when the value of the ramp signal becomes equal to a predetermined value.

Claim 39

A synthesizer according to claim 35 wherein the phase correction means comprises: logic means, electrically connected to the random signal selector, responsive to the random signal to generate a phase correction signal proportional to the interval of time between successive jittered pulses; and scaling means, in electrical communication with the logic means, operative to provide the phase corrected control signal by scaling the externally provided control signal in proportion to the phase correction signal.

Claim 40

Dual clock aliasing reducing signal processing apparatus comprising: first jittered pulse means, operative to provide a first sequence of jittered pulses, each pulse occurring during a predefined portion of one of a first sequence of time intervals of duration 2T at a time determined by a sequential one of a first set of independent random numbers having a uniform probability density in a region bounded by zero and T; second jittered pulse means, operative to provide a second sequence of jittered pulses, each pulse occurring during a predefined portion of one of a second sequence of time intervals of duration 2T at a time determined by a sequential one of a second set of independent random numbers having a uniform probability density in a region bounded by zero and T, said second sequence of time intervals having a predetermined phase relationship with the first sequence of time intervals; first processing means, in electrical communication with the first jittered pulse means, operative to perform a signal processing operation in response to jittered pulses of the first sequence; and second processing means, in electrical communication with the second jittered pulse means, operative to perform a signal processing operation in response to jittered pulses of the second sequence.

Claim 41

Dual clock aliasing reducing signal processing apparatus comprising: first jittered pulse means, operative to provide a first sequence of jittered pulses, each pulse occurring during a predefined portion of one of a first sequence of time intervals of duration 2T at a time determined by a sequential one of a first set of independent random numbers having a uniform probability density in a region bounded by zero and T; second jittered pulse means, operative to provide a second sequence of jittered pulses, each pulse occurring during a predefined portion of one of a second sequence of time intervals of duration 2T at a time determined by a sequential one of a second set of independent random numbers having a uniform probability density in a region bounded by zero and T, said second sequence of time intervals having a predetermined phase relationship with the first sequence of time intervals; first processing means, in electrical communication with the first jittered pulse means, operative to perform a signal processing operation in response to jittered pulses of the first sequence; and second processing means, in electrical communication with the second jittered pulse means, operative to perform a signal processing operation in response to jittered pulses of the second sequence.

Claim 42

Apparatus according to claim 37 wherein the first set of random numbers are indicated by a random signal provided by a random signal generator, the generator comprising: a noise source, operative to provide a noise signal having a randomly varying value; a reference source, operative to provide a reference signal; reference signal correction means, having a first input in electrical communication with the noise source and a second input in electrical communication with the reference source, operative to generate a correction signal if the absolute value of the difference between the noise signal and the reference signal exceeds a bracket amount, the correction signal tending to change the value of the reference signal so as to reduce the absolute value of said difference; and comparator means, in electrical communication with the noise source and the reference source, operative to provide the random signal by comparing the value of the reference signal with the value of the noise signal.

Claim 43

Apparatus according to claim 37 and further comprising a clock source, operative to provide a first sequence of clock pulses having a period of duration 2T and a second sequence of clock pulses having a like period and having a predetermined phase relationship to the first sequence.

Claim 44

Apparatus according to claim 39 wherein the first jittered pulse means comprises first delay means, in electrical communication with the clock source, operative to provide the first sequence of jittered pulses by delaying sequential ones of the first sequence of clock pulses for sequential ones of a set of time intervals determined by the first set of random numbers.

Claim 45

Apparatus according to claim 37 wherein the first jittered pulse means comprises digital processing means.

Claim 46

Apparatus according to claim 37 wherein: the first processing means comprises first sampling means for sampling an input signal, operative to provide a first output signal indicative of the value of the input signal when a jittered pulse of the first sequence is provided; and the second processing means comprises second sampling means for sampling the input signal, operative to provide a second output signal indicative of the value of the input signal when a jittered pulse of the second sequence is provided.

Claim 47

Apparatus according to claim 42 and further comprising logic means for providing a signal indicative of the times at which the jittered pulses are provided.

Claim 48

Apparatus according to claim 37 wherein: the first processing means comprises first synthesis means, operative to synthesize a first output signal having a frequency as specified by an externally provided control signal; and the second processing means comprises second synthesis means, operative to synthesize a second output signal having a frequency as specified by the control signal.

Claim 49

Apparatus according to claim 37 and further comprising: first phase correction means, in electrical communication with the first jittered pulse means, operative to provide a first phase corrected control signal by scaling an externally provided control signal according to the time intervals between sequential ones of the first sequence of jittered pulses; and second phase correction means, in electrical communication with the second jittered pulse means, operative to provide a second phase corrected control signal by scaling the externally provided control signal according to the time intervals between sequential ones of the second sequence of jittered pulses.

Claim 50

Apparatus according to claim 45 wherein: the first processing means comprises first synthesis means, operative to synthesize a first output signal having a frequency as specified by the first phase corrected control signal; and the second processing means comprises second synthesis means, operative to synthesize a second output signal having a frequency as specified by the second phase corrected control signal.

Claim 51

Apparatus according to claim 46 and further comprising output logic means electrically connected to with the first and second processing means, responsive to the first and second output signals to provide a final output signal.

Claim 52

Apparatus according to claim 46 wherein the first synthesis means comprises an accumulator.

Claim 53

Apparatus according to claim 46 wherein the first synthesis means comprises a fractional divider.

Claim 54

Apparatus according to claim 46 and further comprising phase interpolator means.

Claim 55

Apparatus according to claim 46 and further comprising sine wave generation means.

Claim 58

A method according to claim 52 wherein the processing operation comprises sampling an input signal.

Claim 59

A method according to claim 52 wherein the processing operation comprises synthesizing a signal having a desired frequency.

Claim 60

A dual-clock method of reducing aliasing in processing a signal, the method comprising: providing a first sequence of jittered pulses, each pulse occurring during a predefined portion of one of a first sequence of time intervals of duration 2T at a time determined by a sequential one of a first set of independent random numbers having a uniform probability density in a region bounded by zero and T; providing a second sequence of jittered pulses, each pulse occurring during a predefined portion of one of a second sequence of time intervals of duration 2T at a time determined by a sequential one of a second set of independent random numbers having a uniform probability density in a region bounded by zero and T, said second sequence of time intervals having a predetermined phase relationship with the first sequence of time intervals; performing a signal processing operation in response to the first sequence of jittered pulses; and performing said signal processing operation in response to the second sequence of jittered pulses.

Claim 61

A dual-clock method of reducing aliasing in processing a signal, the method comprising: providing a first sequence of jittered pulses, each pulse occurring during a predefined portion of one of a first sequence of time intervals of duration 2T at a time determined by a sequential one of a first set of independent random numbers having a uniform probability density in a region bounded by zero and T; providing a second sequence of jittered pulses, each pulse occurring during a predefined portion of one of a second sequence of time intervals of duration 2T at a time determined by a sequential one of a second set of independent random numbers having a uniform probability density in a region bounded by zero and T, said second sequence of time intervals having a predetermined phase relationship with the first sequence of time intervals; performing a signal processing operation in response to the first sequence of jittered pulses; and performing said signal processing operation in response to the second sequence of jittered pulses.

Claim 62

A method according to claim 55 wherein the processing operation comprises an input signal.

Claim 63

A method according to claim 55 wherein the processing operation comprises synthesizing a signal having a desired frequency.