ECL to CMOS converter

Claim 2

An ECL to CMOS converter for converting high or low ECL logic signals appearing at the output of an ECL circuit comprising: a CMOS inverter for providing low or high CMOS logic signals at its output in response to a first or second signal, respectively, applied to its input, wherein said first signal must exceed a first predetermined value and said second signal must fall below a second predetermined value, and wherein said low ECL signal does not fall below said second predetermined value; and means for converting said high and low ECL logic signals to said first and second signals, respectively, wherein said converting means includes: a transfer gate connecting said ECL circuit output to said CMOS inverter input; a control circuit for providing at an output thereof a control voltage which varies proportionally with changes in said ECL logic signals, wherein said control circuit output is connected to the control electrode of said transfer gate; and resistive means connected between said CMOS inverter input and a first power supply terminal which provides a first CMOS reference voltage.

Claim 3

The ECL to CMOS converter of claim 1 wherein said transfer gate is a first PMOS field effect transistor with its source connected to said ECL circuit output, its drain connected to said CMOS inverter input and its gate connected to said control circuit output, and wherein the resistance of said PMOS transistor changes with the ECL logic signal applied to its source so that its resistance is relatively low compared to that of said resistive means for the high ECL logic signal and is relatively high compared to that of said resistive means for the low ECL logic signal.

Claim 4

The ECL and CMOS converter of claim 2 wherein said resistive means is an NMOS field effect transistor with its drain connected to said CMOS inverter input, its source connected to said first power supply terminal and its gate connected to a second power supply terminal which provides a second CMOS reference voltage.

Claim 5

The ECL to CMOS converter of claim 3 wherein said CMOS inverter is connected between said second and first power supply terminals.

Claim 6

The ECL to CMOS converter of claim 1 wherein said control circuit comprises: a reference voltage generator circuit for providing a reference voltage at an output thereof, said generator circuit being positioned in the same temperature environment as said ECL circuit.

Claim 7

The ECL to CMOS converter of claim 5 wherein said control circuit further comprises: a converting circuit for converting said reference voltage to said control voltage, said converting circuit being connected between said output of the reference voltage generator circuit and said control circuit output.

Claim 8

The ECL to CMOS converter of claim 6 wherein said converting circuit comprises: a second PMOS field effect transistor with its drain connected to said output of the reference voltage generator circuit, its source connected to said control circuit output, and its gate connected to its source.

Claim 9

The ECL to CMOS converter of claim 7 wherein said converting circuit further comprises a resistor connected between said source of said second PMOS transistor and said first power supply terminal.

Claim 10

The ECL to CMOS converter of claim 5 wherein said reference voltage generator circuit comprises an ECL logic NOR circuit having two inputs with said generator circuit output connected to one of said inputs.

Claim 11

An ECL to CMOS converter for converting high or low ECL logic signals appearing at the output of an ECL circuit comprising: a CMOS inverter for providing low or high CMOS logic signals at its output in response to a first or second signal, respectively, applied to its input, wherein said first signal must exceed a first predetermined value and said second signal must fall below a second predetermined value, and wherein said high ECL signal does not exceed said first predetermined value; and means for converting said high and low ECL logic signals to said first and second signals, respectively, wherein said converting means comprises: a transfer gate connecting said ECL circuit output to said CMOS inverter input; a control circuit for providing at an output thereof a control voltage which automatically compensates for changes in said ECL logic signals, wherein said control circuit output is connected to the control electrode of said transfer gate; and resistive means connected between said CMOS inverter input and a first power supply terminal which provides a first CMOS reference voltage.

Claim 12

An ECL to CMOS converter for converting high or low ECL logic signals appearing at the output of an ECL circuit comprising: a CMOS inverter for providing low or high CMOS logic signals at its output in response to a first or second signal, respectively, applied to its input, wherein said first signal must exceed a first predetermined value and said second signal must fall below a second predetermined value, and wherein said high ECL signal does not exceed said first predetermined value; and means for converting said high and low ECL logic signals to said first and second signals, respectively, wherein said converting means comprises: a transfer gate connecting said ECL circuit output to said CMOS inverter input; a control circuit for providing at an output thereof a control voltage which automatically compensates for changes in said ECL logic signals, wherein said control circuit output is connected to the control electrode of said transfer gate; and resistive means connected between said CMOS inverter input and a first power supply terminal which provides a first CMOS reference voltage.

Claim 13

The ECL to CMOS converter of claim 10 wherein said transfer gate is a first PMOS field effect transistor with its source connected to said ECL circuit output, its drain connected to said CMOS inverter input and its gate connected to said control circuit output, and wherein the resistance of said PMOS transistor changes with the ECL logic signal applied to its source so that its resistance is relatively low compared to that of said resistive means for the high ECL logic signal and is relatively high compared to that of said resistive means for the low ECL logic signal.

Claim 14

The ECL to CMOS converter of claim 11 wherein said resistive means is an NMOS field effect transistor with its drain connected to said CMOS inverter input, its source connected to said first power supply terminal and its gate connected to a second power supply terminal which provides a second CMOS reference voltage.

Claim 15

The ECL to CMOS converter of claim 12 wherein said CMOS inverter is connected between said second and first power supply terminals.

Claim 16

The ECL to CMOS converter of claim 10 wherein said control circuit comprises: a reference voltage generator circuit for providing a reference voltage at an output thereof, said generator circuit being positioned in the same temperature environment as said ECL circuit.

Claim 17

The ECL to CMOS converter of claim 14 wherein said control circuit further comprises: a converting circuit for converting said reference voltage to said control voltage, said converting circuit being connected between said output of the reference voltage generator circuit and said control circuit output.

Claim 18

The ECL to CMOS converter of claim 15 wherein said converting circuit comprises: a second PMOS field effect transistor with its drain connected to said output of the reference voltage generator circuit, its source connected to said control circuit output, and its gate connected to its source.

Claim 19

The ECL to CMOS converter of claim 16 wherein said converting circuit further comprises a resistor connected between said source of said second PMOS transistor and said first power supply terminal.

Claim 20

The ECL to CMOS converter of claim 14 wherein said reference voltage generator circuit comprises an ECL logic NOR circuit having two inputs with said generator circuit output connected to one of said inputs.

Claim 21

An ECL to CMOS converter for converting high or low ECL logic signals appearing at the output of an ECL circuit comprising: a CMOS inverter connected between first and second power supply terminals for providing low or high CMOS logic signals at its output in response to a first or second signal, respectively, applied to its input, wherein said first signal must exceed a first predetermined value and said second signal must fall below a second predetermined value, and wherein said low ECL signal does not fall below said second predetermined value; and means for converting said high and low ECL logic signals to said first and second signals, respectively, said means including: a reference voltage generator circuit for providing a reference voltage at an output thereof, said generator circuit being positioned in the same temperature environment as said ECL circuit; a converting circuit, connected to the output of the reference voltage generator circuit, for converting said reference voltage to a control voltage at an output thereof; an NMOS field effect transistor with its drain connected to said CMOS inverter input, its source connected to said first power supply terminal and its gate connected to said second power supply terminal; and a first PMOS filed effect transistor with its source connected to said ECL circuit output, its drain connected to said CMOS inverter input and its gate connected to said converting circuit output, and wherein the resistance of said PMOS transistor changes with the ECL logic signal applied to its source so that its resistance is relatively low compared to that of said NMOS transistor for the high ECL logic signal and is relatively high compared to that of said NMOS transistor for the low ECL logic signal.

Claim 22

An ECL to CMOS converter for converting high or low ECL logic signals appearing at the output of an ECL circuit comprising: a CMOS inverter connected between first and second power supply terminals for providing low or high CMOS logic signals at its output in response to a first or second signal, respectively, applied to its input, wherein said first signal must exceed a first predetermined value and said second signal must fall below a second predetermined value, and wherein said low ECL signal does not fall below said second predetermined value; and means for converting said high and low ECL logic signals to said first and second signals, respectively, said means including: a reference voltage generator circuit for providing a reference voltage at an output thereof, said generator circuit being positioned in the same temperature environment as said ECL circuit; a converting circuit, connected to the output of the reference voltage generator circuit, for converting said reference voltage to a control voltage at an output thereof; an NMOS field effect transistor with its drain connected to said CMOS inverter input, its source connected to said first power supply terminal and its gate connected to said second power supply terminal; and a first PMOS filed effect transistor with its source connected to said ECL circuit output, its drain connected to said CMOS inverter input and its gate connected to said converting circuit output, and wherein the resistance of said PMOS transistor changes with the ECL logic signal applied to its source so that its resistance is relatively low compared to that of said NMOS transistor for the high ECL logic signal and is relatively high compared to that of said NMOS transistor for the low ECL logic signal.

Claim 23

The ECL to CMOS converter of claim 19 wherein said converting circuit comprises: a second PMOS field effect transistor with its drain connected to said output of the reference voltage generator circuit, its source connected to said converting circuit output, and its gate connected to its source.

Claim 24

The ECL to CMOS converter of claim 20 wherein said converting circuit further comprises a resistor connected between said source of said second PMOS transistor and said first power supply terminal.

Claim 25

The ECL to CMOS converter of claim 21 wherein said reference voltage generator circuit comprises an ECL logic NOR circuit having two inputs with said generator circuit output connected to one of said inputs.