Apparatus and method for performing a shift operation in a multiplier array circuit

Claim 2

Apparatus for shifting a group of logic signals a controllable number of positions to the right, said apparatus comprising: a multiplier unit including; a first operand register for storing a multiplicand operand, a second operand register for storing a multiplier operand, a plurality of sequential stages including carry/save adder units, each of said carry/save adder unit stages receiving logic signals from a next previous stage and from said first operand register, an encoding unit coupled to each stage and responsive to logic signals from selected positions of said second operand register, said encoding unit providing control signals to said coupled carry/save adder stage, said control signals causing said coupled carry/save adder stage to process logic signals from a next previous carry/save adder unit stage and from said first operand register in a predetermined manner, wherein paths between a carry/save adder unit stage and a next sequential carry/save adder unit stage include signal paths for shifting logic signals at least one bit position; and conversion means for converting a shift operand indicating a number of positions said group of logic signals is to be shifted into shift signals to be applied to said encoding means, said group of logic signals being entered in said first operand register, wherein control signals generated in response to said shift signals cause said group of logic signals to be shifted said number of positions.

Claim 3

The shifting apparatus is implemented to execute a two bit retirement algorithm to perform a multiplication operation.

Claim 4

The shifting apparatus is implemented to execute a two bit retirement algorithm to perform a multiplication operation.

Claim 5

The shifting apparatus of claim 2 wherein each of said carry/save adder unit stages responds to a first set of control signals by passing a partial sum through said each carry/save adder unit stage without a processing operation, said each carry/save adder unit stage responding to a second control signal by adding one time said first operand register logic signals to a partial product applied to said each carry/save adder unit stage from a next previous carry/save adder unit stage, said each carry/save adder unit stage responsive to said second and to a third control signal for adding two times said first operand register logic signals to a partial product applied to said each carry/save adder unit stage from a next previous carry/save adder unit stage.

Claim 6

The shifting apparatus of claim 3 wherein said multiplier unit provides a one bit position shifting apparatus following a final carry/save adder unit stage.

Claim 7

The shifting apparatus of claim 1 further comprising multiple pass means for permitting said group of logic signals to be shifted by said multiplier unit a plurality of times, wherein output signals from said multiplier unit are applied to an input carry/save adder stage of said multiplier unit by said multiple pass means.

Claim 10

The method of claim 6 further including the step of implementing said multiplier unit with apparatus performing a multiplication operation by a retirement algorithm for a group of logic signals in said multiplier register.

Claim 11

The method of claim 7 further including a step of cycling said logic signal group through said multiplier unit a plurality of times.

Claim 12

The method of claim 7 wherein said step of executing said operation includes the steps of passing a partial product through a carry/save adder stage without processing, adding said logic signal group to a carry/save adder stage, and shifting said logic signal group one position in an opposite direction from said preselected number of positions.

Claim 13

The method of claim 9 wherein said executing step can include an adding step and a shifting step performed by a same carry/save adder stage.

Claim 14

Apparatus for performing a controllable shift operation on a data signal group, said apparatus comprising: first register means for storing said data signal group; a plurality of carry/save arrays, each carry/save array including: a multiplicity of carry/save adder units; and a selector circuit connected to with each carry/save adder unit for selecting either an input signal from a corresponding bit position of said first register means or an input signal from a neighboring position of said corresponding bit position; each of said carry/save adder units providing a sum output signal and a carry output signal in response to a carry input signal, a sum input signal and a selected signal from said connected selector circuit; wherein output signals from a carry/save array are input signals for a next sequential carry/save array, said input signals being applied to a carry/save adder unit shifted a predetermined number of bit positions when applied to said next sequential carry/save array; and a plurality of control means, each of said control means coupled to a carry/save adder array, said each control means for applying control signals to said coupled carry/save array for providing preselected operations on carry/save input signals; and a second register means coupled to said plurality of control means, a multiplier operand in said second register means causing said carry/save arrays to perform said selected operations in a manner to provide a product of said data signal group and said multiplier operand in a first mode of operation, a shift operand in said second register means causing said data signal group to be shifted a predetermined number of positions in a second mode of operation.

Claim 15

Apparatus for performing a controllable shift operation on a data signal group, said apparatus comprising: first register means for storing said data signal group; a plurality of carry/save arrays, each carry/save array including: a multiplicity of carry/save adder units; and a selector circuit connected to with each carry/save adder unit for selecting either an input signal from a corresponding bit position of said first register means or an input signal from a neighboring position of said corresponding bit position; each of said carry/save adder units providing a sum output signal and a carry output signal in response to a carry input signal, a sum input signal and a selected signal from said connected selector circuit; wherein output signals from a carry/save array are input signals for a next sequential carry/save array, said input signals being applied to a carry/save adder unit shifted a predetermined number of bit positions when applied to said next sequential carry/save array; and a plurality of control means, each of said control means coupled to a carry/save adder array, said each control means for applying control signals to said coupled carry/save array for providing preselected operations on carry/save input signals; and a second register means coupled to said plurality of control means, a multiplier operand in said second register means causing said carry/save arrays to perform said selected operations in a manner to provide a product of said data signal group and said multiplier operand in a first mode of operation, a shift operand in said second register means causing said data signal group to be shifted a predetermined number of positions in a second mode of operation.

Claim 16

The apparatus of claim 11 wherein said multiplier operand is converted by said control means into retirement algorithm control signals causing said carry/save arrays to perform multiplication using a retirement algorithm.

Claim 17

The apparatus of claim 12 wherein said retirement algorithm is a two bit retirement algorithm, said control signals including a control signal for application to said selector circuit.

Claim 18

The apparatus of claim 13 wherein said control signals include a pass control for passing a signal group through a coupled carry/save array without change.

Claim 19

The apparatus of claim 13 wherein said control signals include an enter control signal for entering a data signal group from said first register means in a coupled carry/save array.

Claim 20

The apparatus of claim 11 wherein output signals from a last carry/save array are coupled to input signal terminals of a first carry/save array when a single processing by said plurality of carry/save arrays can not shift said data signal group said predetermined number of positions in said first mode of operation.

Claim 21

The apparatus of claim 16 further comprising a combining network, wherein said last carry/save array output signals are coupled to said combining network, said output sum and said carry output signals being combined to form a product operand in said combining network in said first mode of operation.

Claim 22

The apparatus of claim 17 wherein said plurality of carry/save arrays includes 4 carry/save arrays, wherein said predetermined number is one through seven.

Claim 23

The apparatus of claim 16 wherein a predetermined number greater than seven requires a plurality of processing procedure by said apparatus.