Patent US4303453A successfully refreshed from Google Patents.
US4718031A
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Multiplying circuit
Assignee: NEC Corp
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Filing: 1985-02-04
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Granted: 1988-01-05
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Expires: 2005-02-04
Abstract
Abstract In a multiplying operation, a first partial product corresponding to multiplication of the multiplicand by even multipliers can be produced by a shifting operation, while a second partial product corresponding to multiplication of the multiplicand by odd multipliers is produced by a shifting operation and an adding operation. In the described multiplying circuit, the first partial product is produced according to the result of a decoding operation for generating signals designating the partial product to be used in the multiplying operation. On the other hand the second partial product is independently produced regardless of the decoding result when the multiplicand is received to the multiplying circuit. Thus, a high speed multiplying operation can be achieved.
Inventors
- 👤 Tomoji Nukiyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 01:41
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/533; G06F7/5334; G06F7/5336
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
163 words
A multiplying circuit comprising a first means receiving a multiplicand X, a second means coupled to said first means and producing 3X corresponding to three times said multiplicand X in response to the reception of said multiplicand X, a third means receiving a multiplier Y, a fourth means coupled to said third means and generating at least five signals by decoding said mulltiplier Y, a first signal designating zero, a second signal designating X, a third signal designating 2X, a fourth signal designating 3X, a fifth signal designating 4X, a fifth means coupled to said first and fourth means and producing data 0, X, 2X and 4X according to said first, second, third and fifth signals, a sixth means producing a total sum according to said data 0, X, 2X, 3X and 4X, and seventh means coupled to said second, fourth and sixth means for applying said data 3X to said sixth means when said fourth signal is generated from said fourth means.
Claim 2
Dependent Claim
163 words
A multiplying circuit comprising a first means receiving a multiplicand X, a second means coupled to said first means and producing 3X corresponding to three times said multiplicand X in response to the reception of said multiplicand X, a third means receiving a multiplier Y, a fourth means coupled to said third means and generating at least five signals by decoding said mulltiplier Y, a first signal designating zero, a second signal designating X, a third signal designating 2X, a fourth signal designating 3X, a fifth signal designating 4X, a fifth means coupled to said first and fourth means and producing data 0, X, 2X and 4X according to said first, second, third and fifth signals, a sixth means producing a total sum according to said data 0, X, 2X, 3X and 4X, and seventh means coupled to said second, fourth and sixth means for applying said data 3X to said sixth means when said fourth signal is generated from said fourth means.
Claim 3
Dependent Claim
46 words
A multiplying circuit as claimed in claim 1, in which said second means includes shifting means for shifting the received multiplicand X by 1 bit toward the most significant bit to produce 2X and adding means for adding the produced 2X to said received multiplicand X.
Claim 4
Dependent Claim
74 words
A multiplying circuit as claimed in claim 1, in which said fifth means includes means for outputting the data 0 when said first signal is generated, means for transferring the multiplicand X when said second signal is generated, means for shifting the multiplicand X by 1 bit towards the most significant bit side to produce the data 2X, and means for shifting the multiplicand X by 2 bits towards the most significant bit side.
Claim 5
Dependent Claim
212 words
A multiplying circuit comprising a first input means receiving a multiplicand composed of a plurality of bits, a second input means for receiving a multiplier composed of a plurality of bits, a decoding means coupled to said second input means for decoding said multiplier according to the Booth's algorithm to generate at least a first signal designating a first partial product of a multiplicand and an even number and a second signal designating a second partial product of a multiplicand and an odd number, a second partial product calculating means coupled to said first input means for calculating said second partial product in response to reception of said multiplicand, a first partial product calculating means coupled to said first input means and said decoding means for calculating said first partial product by use of the received multiplicand in response to said first signal generated by said decoding means, transferring means coupled to said second partial product calculating means and said decoding means for transferring said second partial product from said second partial product calculating means in response to said second signal generated from said decoding means, and adding means coupled to said first partial product calculating means and said transferring means for adding said first partial product to said second partial product.
Claim 6
Dependent Claim
212 words
A multiplying circuit comprising a first input means receiving a multiplicand composed of a plurality of bits, a second input means for receiving a multiplier composed of a plurality of bits, a decoding means coupled to said second input means for decoding said multiplier according to the Booth's algorithm to generate at least a first signal designating a first partial product of a multiplicand and an even number and a second signal designating a second partial product of a multiplicand and an odd number, a second partial product calculating means coupled to said first input means for calculating said second partial product in response to reception of said multiplicand, a first partial product calculating means coupled to said first input means and said decoding means for calculating said first partial product by use of the received multiplicand in response to said first signal generated by said decoding means, transferring means coupled to said second partial product calculating means and said decoding means for transferring said second partial product from said second partial product calculating means in response to said second signal generated from said decoding means, and adding means coupled to said first partial product calculating means and said transferring means for adding said first partial product to said second partial product.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1991-01-04 | 1991-07-06 | 1992-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-04 | 1995-07-06 | 1996-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-04 | 1999-07-06 | 2000-01-05 | $7700.00 | Window Closed / Lapsed |