Round off correction logic for modified Booth's algorithm

Claim 1

In a binary digital multiplier implementing a modified Booth's algorithm and having a first stage of a plurality of partial product generators, a second stage of a plurality of summing networks including a first summation network and a second summation network, a third stage including a third summation network, and a fourth stage including a fourth summation network, said multiplier for generating a final product of a series of binary digits, the improvement comprising round off logic circuitry in said multiplier for rounding off to a predetermined nth bit least significant binary digit of said final product without generating the least significant binary digits to the right of said nth bit of said final product said circuitry including in said first stage a plurality of partial product generators for generating partial products from a multiplicand X and multiplier Y including a first least significant bits multiplier generator A, a second next least significant bits multiplier generator B, a third next least significant bits multiplier C and a fourth next least significant bits multiplier generator D (where the numerical subscript following a letter indicates significance of bit position therein); said circuitry including a first carry signal generator stage connected to said partial product generators A and B for generating a first carry signal C[n-1]1 defined as equal to (B[n-2]+A[n-2])·(A[n-2]+B[n-3]+A[n-3])·(A[n-3]+B[n-3]+B[n-2]) and supplying said first carry signal C[n-1]1 to said first summation network; said circuitry including a second carry signal generator stage connected to said partial product generators C and D for generating a second carry signal C[n-1]3 defined as equal to (C[n-2]+C[n-3]+D[n-2]+Y[n-1])·(C[n-2]+C[n-3]+Y[n-1])·(C[n-2]+C[n-3]+D[n-2])·(C[n-3]+D[n-2]+Y[n-1]) and supplying said second carry signal C[n-1]3 to said second summation network; said circuitry including a third carry signal generator stage connected to said partial product generators for generating a third carry signal C[n-1]4 defined as equal to C[n-2]·D[n-2]·Y[n-1]·C[n-3] where Y[n-1] is a multiplier bit two bit positions to the right of the nth bit position of the multiplier, and supplying said third carry signal C[n-1]4 to said third summation network; said circuitry including a fourth carry signal generator and least significant bit final rounded product generator stage connected to said partial product generators and to said third summation network for generating a fourth carry signal C[n]1 defined as equal to W[n-1]·(S[n-2]1+S[n-2]2) and a least significant bit rounded product output Pn defined as equal to W[n-1] + (S[n-2]1+S[n-2]2) where W[n-1] is the least significant bit carry signal from the third summation network, S[n-2]1 is defined as equal to A[n-2]·[B[n-2] + (A[n-3]+B[n-3])]+A[n-2]·[B[n-2] + (A[n-3]+B[n-3])] and S[n-2]2 is defined as equal to C(n-2)·[D[n-2] + Y[n-1] + C[n-3]]+C[n-2]·[D[n-2] + Y[n-1] + C[n-3]] and supplying said fourth summation network with said fourth carry signal and providing said least significant bit rounded product output Pn at the output of said multiplier.