US3885141A
Expired / Lapsed
US
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Modular pipeline multiplier to generate a rounded product
Assignee: AT&T Inc
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Filing: 1974-02-06
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Granted: 1975-05-20
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Expires: 1994-02-06
Abstract
Abstract A serial digital multiplier includes m identical cascaded stages for generating the rounded product of an n-bit binary data word and an m-bit binary coefficient word. The multiplier further includes means for applying a logic 1 signal to the first stage to effect rounding of the final product at the output of the multiplier.
Inventors
- 👤 Robert Bruce Kieburtz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 02:33
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/527; G06F7/5277; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3884; G06F7/499; G06F7/49942; G06F7/49947; G06F7/49963
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
235 words
A pipeline digital multiplier circuit for forming the rounded product of an n-bit data word and an m-bit coefficient word comprising a. m identical stages, each comprising i. first, second and third input terminals and an output terminal, ii. means for applying a uniquely associated bit of said coefficient word to said first input terminal, iii. means for forming during the ith time interval the bit product of said bit applied at said first input terminal with a data bit applied at said second input terminal, iv. means for generating a sum signal by adding said bit product to a bit representative of a partial product generated during the (i-1)th time interval and a bit representative of carry signals from previous additions, v. means for selectively inhibiting said sum signal to eliminate those sum signals which contribute only to one of the bits of the truncated portion of the product of said data word and said coefficient word, vi. means for applying said selectively inhibited sum signal to said output terminal, b. means for connecting the output terminal of each stage but the last to the third input terminal of the next succeeding stage, c. means for sequentially applying said n-bit data word to the second input terminal of the first of said stages, and d. means for applying a logic 1 signal to said means for generating a sum signal in said first stage.
Claim 2
Dependent Claim
235 words
A pipeline digital multiplier circuit for forming the rounded product of an n-bit data word and an m-bit coefficient word comprising a. m identical stages, each comprising i. first, second and third input terminals and an output terminal, ii. means for applying a uniquely associated bit of said coefficient word to said first input terminal, iii. means for forming during the ith time interval the bit product of said bit applied at said first input terminal with a data bit applied at said second input terminal, iv. means for generating a sum signal by adding said bit product to a bit representative of a partial product generated during the (i-1)th time interval and a bit representative of carry signals from previous additions, v. means for selectively inhibiting said sum signal to eliminate those sum signals which contribute only to one of the bits of the truncated portion of the product of said data word and said coefficient word, vi. means for applying said selectively inhibited sum signal to said output terminal, b. means for connecting the output terminal of each stage but the last to the third input terminal of the next succeeding stage, c. means for sequentially applying said n-bit data word to the second input terminal of the first of said stages, and d. means for applying a logic 1 signal to said means for generating a sum signal in said first stage.
Claim 3
Dependent Claim
30 words
Apparatus as in claim 1 wherein said means for generating a sum signal in each of said stages includes storage means for storing a signal representative of a carry bit.
Claim 4
Dependent Claim
18 words
Apparatus as in claim 2 wherein said means for forming the bit product comprises a first AND gate.
Claim 5
Dependent Claim
38 words
Apparatus as in claim 3 wherein said means for inhibiting includes a second AND gate having first and second input terminals and means for selectively applying a logic 0 to one of said second AND gate input terminals.
Claim 6
Dependent Claim
246 words
A serial multiplier for generating a set of n binary signals corresponding to the n most significant bits of the product of an n-bit binary data word and an m-bit binary coefficient word, comprising a. an ordered plurality of m identical stages, Si, i 1,2, . . . m, where S1, is the input stage and Sm is the output stage, b. means for simultaneously applying each of an ordered set of binary signals bi, i 1,2, . . . m, to respective ones of said stages each bi representing a bit of said coefficient word where the (bi 1)th signal corresponds to the next more significant bit position than the (bi)th signal, c. means for applying in sequence an ordered set of signals, aj, j 1,2, . . . n, to said first multiplier stage where the signal aj corresponds to the jth bit of said binary data word and where the least significant bit signal a1, is applied first, d. said ith stage, i 1,2, . . . m, comprising, i. a first AND gate for generating signals corresponding to the logical AND operation on said binary coefficient word signal bi and one of said binary data word signals aj, ii. means for summing signals generated by said first AND gate with selected ones of the signals at the output of the (i-1)st multiplier stage, and e. means for periodically applying a logical 1 signal to said means for summing in said first stAge.
Claim 7
Dependent Claim
246 words
A serial multiplier for generating a set of n binary signals corresponding to the n most significant bits of the product of an n-bit binary data word and an m-bit binary coefficient word, comprising a. an ordered plurality of m identical stages, Si, i 1,2, . . . m, where S1, is the input stage and Sm is the output stage, b. means for simultaneously applying each of an ordered set of binary signals bi, i 1,2, . . . m, to respective ones of said stages each bi representing a bit of said coefficient word where the (bi 1)th signal corresponds to the next more significant bit position than the (bi)th signal, c. means for applying in sequence an ordered set of signals, aj, j 1,2, . . . n, to said first multiplier stage where the signal aj corresponds to the jth bit of said binary data word and where the least significant bit signal a1, is applied first, d. said ith stage, i 1,2, . . . m, comprising, i. a first AND gate for generating signals corresponding to the logical AND operation on said binary coefficient word signal bi and one of said binary data word signals aj, ii. means for summing signals generated by said first AND gate with selected ones of the signals at the output of the (i-1)st multiplier stage, and e. means for periodically applying a logical 1 signal to said means for summing in said first stAge.
Claim 8
Dependent Claim
24 words
Apparatus as in claim 5 wherein said ith stage further includes a second AND gate for selectively inhibiting signals generated by said summing means.
Claim 9
Dependent Claim
22 words
Apparatus as in claim 6 wherein said ith stage further includes storage means for storing carry signals generated by said summing means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-19 | 1978-11-18 | 1979-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-19 | 1982-11-18 | 1983-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-19 | 1986-11-18 | 1987-05-20 | $7700.00 | Window Closed / Lapsed |