Multipurpose serial/parallel multiplier

Claim 3

The invention according to claim 1, wherein the most-significant bit of the n-bit number is applied to the nth multiplicand input terminal means with the least-significant bit applied to the 1-multiplicand terminal means; and wherein the least-significant bit of the m-bit number is applied first to the multiplier''s input means.

Claim 4

The invention according to claim 1 wherein said delay means retards a received bit for one clock time.

Claim 5

The invention according to claim 1 wherein said sign spread circuit comprises: a. an AND gate having one input terminal connected to said multiplier input means, and another input terminal connected to receive a signal indicative of said multiplier sign bit; b. a flip-flop connected to be activated to one state by the output of said AND gate and to be activated to another state by a timing pulse originating during the last bit of the product of said multiplier and said multiplicand; c. an OR gate having one input terminal connected to said multiplier input means, and another input terminal connected to the output of said flip-flop; and d. the output of said OR gate of said sign-spread circuit connected to one input of each of said n-number of gates.

Claim 6

A serial/parallel multiplication device comprising in combination: a. an n-number of multiplicand input terminals for receiving an n-bit number in parallel with the nth bit of said number being the most-significant bit which is applied to the n-terminal and the one-bit of said number being the least-significant bit applied to the 1-terminal; b. a serial input terminal, for receiving multiplier bits serially with the least-significant bit of said multiplier appearing first; c. at least an n-number of gates, with each gate receiving one bit from a corresponding multiplicand input terminal and with each gate receiving the bits from said serial input terminal; d. a sign spread circuit interposed between said serial input terminal and said n-number of gates for spreading the sign bit of an input serial number; e. a plurality of adder means serially connected to each other and each connected to receive the output from one gate exclusive of a first gate; f. a first delay means connected to the output of said first gate; g. an inverter connected between a first adder and the said first delay means; h. delay means interposed between each adder means for delaying the output from a preceding adder means and gate by one clock time; i. a plurality of delay means connected in feedback relationship around each adder means for delaying the carry bit of said adder for one clock period; and j. an OR gate interposed between the output of said first adder''s delay means and the input of said first adder, one input of said OR gate adapted to receive a timing pulse during generation of the least-significant bit of the product of said multiplier and said multiplicand.

Claim 7

A serial/parallel multiplication device comprising in combination: a. an n-number of multiplicand input terminals for receiving an n-bit number in parallel with the nth bit of said number being the most-significant bit which is applied to the n-terminal and the one-bit of said number being the least-significant bit applied to the 1-terminal; b. a serial input terminal, for receiving multiplier bits serially with the least-significant bit of said multiplier appearing first; c. at least an n-number of gates, with each gate receiving one bit from a corresponding multiplicand input terminal and with each gate receiving the bits from said serial input terminal; d. a sign spread circuit interposed between said serial input terminal and said n-number of gates for spreading the sign bit of an input serial number; e. a plurality of adder means serially connected to each other and each connected to receive the output from one gate exclusive of a first gate; f. a first delay means connected to the output of said first gate; g. an inverter connected between a first adder and the said first delay means; h. delay means interposed between each adder means for delaying the output from a preceding adder means and gate by one clock time; i. a plurality of delay means connected in feedback relationship around each adder means for delaying the carry bit of said adder for one clock period; and j. an OR gate interposed between the output of said first adder''s delay means and the input of said first adder, one input of said OR gate adapted to receive a timing pulse during generation of the least-significant bit of the product of said multiplier and said multiplicand.

Claim 8

The invention according to claim 5 wherein said sign spread circuit is comprised of: a. an AND gate having one input terminal connected to said serial input terminal, and another input terminal connected to receive a signal indicative of said multiplier sign bit; b. a flip-flop connected to be activated to one state by the output of said AND gate and to be activated to another state by the last bit of the product of said multiplier and said multiplicand; c. an OR gate having one input terminal connected to said multiplier input means, and another inputs terminal connected to the output of said flip-flop; and d. the output of said OR gate of said sign spread circuit connected to an input of each of said n-number of gates.

Claim 9

A multiplication device comprising: a. means for applying an n-bit multiplicand number in parallel; b. means for applying an m-bit multiplier number serially; c. one bit of said multiplier and said multiplicand number indicative of the sign of the respective numbers; d. means for simultaneously multiplying each bit of said multiplicand by a bit of said multiplier to provide partial products; e. a shifting register means receiving said partial products providing an output indicative of the product of said multiplicand and said multiplier; f. means for providing in cooperation with said sign bits an output indicative of the product sign; and g. said means for providing an output indicative of said product sign including sign spread means interposed between said means for applying said multiplier bit number serially and said means for simultaneously multiplying each bit of said multiplicand by a bit of said multiplier.

Claim 10

A multiplication device comprising: a. means for applying an n-bit multiplicand number in parallel; b. means for applying an m-bit multiplier number serially; c. one bit of said multiplier and said multiplicand number indicative of the sign of the respective numbers; d. means for simultaneously multiplying each bit of said multiplicand by a bit of said multiplier to provide partial products; e. a shifting register means receiving said partial products providing an output indicative of the product of said multiplicand and said multiplier; f. means for providing in cooperation with said sign bits an output indicative of the product sign; and g. said means for providing an output indicative of said product sign including sign spread means interposed between said means for applying said multiplier bit number serially and said means for simultaneously multiplying each bit of said multiplicand by a bit of said multiplier.