US3794820A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Binary multiplier circuit
Assignee: Lanteris Space LLC
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Filing: 1972-10-16
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Granted: 1974-02-26
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Expires: 1992-10-16
Abstract
Abstract A fast binary multiplier in the form of a matrix of partial product generators and addition circuits wherein the number of columns of the matrix corresponds to the largest number of digits in the multiplicand and the number of rows in the matrix corresponds to the largest number of digits of the multiplier for which the multiplier is designed. The multiplier is constructed much like a parallel multiplier but operates like a serial multiplier.
Inventors
- 👤 J Robinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:38
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/53; G06F7/5306; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/388; G06F2207/3884
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
971 words
A binary multiplier circuit for multiplying together a multiplier and a multiplicand, the respective digits of each of said multiplier and said multiplicand being represented by respective signals supplied at respectively different input terminals at respectively different times, the signal representative of the lowest order one of said digits in each of said multiplier and multiplicand being supplied at the earliest of said different times and the signals respectively representative of the successively higher-order ones of said digits being supplied at successively later times, adjacent ones of said different times being separated by one time unit, said circuit comprising: a. first means for supplying each of said multiplier-digitrepresentative signals at each of a first number of specified successive times, said first number being equal to the number of digits in said multiplicand, and adjacent ones of said specified successive times being spaced by said one time unit; b. second means for supplying each of said multiplicand-digitrepresentative signals at each of a second number of given successive times, said second number being equal to the number of digits in said multiplier, and adjacent ones of said given successive times being spaced by two of said time units; c. a row of partial product generators for each digit of said multiplier, each row having an order corresponding to the order of the Corresponding digit of said multiplier, each of said rows of partial product generators having a number of partial product generators equal to the number of digits in said multiplicand, each partial product generator in each of said rows having a position in that row corresponding to the order of the corresponding digit of said multiplicand, each of said partial product generators having means for receiving a first input and a second input and for producing an output; d. means coupled to said first means, for supplying, at successive times separated by one of said time units, that one of said signals which is representative of a digit of given order of said multiplier, to said first input of successive ones of said partial product generators located in that row of partial product generators corresponding to said given order; e. means coupled to said second means, for supplying, at successive times separated by two of said time units, that one of said signals which is representative of a digit of specified order of said multiplicand, to said second input of successive ones of said partial product generators located, in said rows of partial product generators, in respective positions corresponding to said specified order; f. a plurality of ordered rows of addition circuit arranged so that the lowest order row of addition circuits corresponds to the second lowest order digit of said multiplier, there being one less row of addition circuits than there are rows of partial product generators, each addition circuit in each of said rows of addition circuits having a position in that row corresponding to the order of the corresponding digit of said multiplicand, each of said addition circuits having means for receiving a first input and for providing a sum output and a carry output, each of said addition circuits except the highest order addition circuit in said lowest order row of addition circuits having means for receiving a second input, and each of said addition circuits except the addition circuit in the lowest-order position in each row of addition circuits having means for receiving a carry input; g. each of said addition circuits except the addition circuit in the lowest-order position in each of said rows of addition circuits being connected to receive a carry input from the addition circuit in the next-lower order position in said row, means for supplying to addition circuits in said lowest order row of addition circuits, as said second input, the outputs of the partial product generators of respectively corresponding position in the second lowest order row of partial product generators, and means for supplying to each addition circuit in said lowest order row of addition circuits except the addition circuit in the highest-order position in that row, as said first input, the output of the partial product generator in the next-higher-order position in the lowest order row of partial product generators; each of said addition circuits in the remaining rows of addition circuits corresponding to the third and higher order digits of said multiplier being connected to receive as a first input the output of the partial product generator in the same position in the same order row of partial product generators; all addition circuits except the addition circuit in the highest order position in each of said remaining rows of addition circuits being connected to receive as a second input the sum output of the addition circuit in the next-higher-order position in the next lower order row of addition circuits; and the order addition circuit in the highest-order position in each of the said remaining rows of addition circuits being connected to receive as a second input the carry output of the addition circuit in the highest-order position in the previous row of addition circuits; h. and a plurality of output terminals, the highest order output terminal being connected to the carry output of the addition circuit in the highest-order pOsition in the highest order row of addition circuits, each of said sum outputs of each of said addition circuits in the highest order row of addition circuits being connected to a corresponding one of said output terminals, each of said sum outputs of the addition circuits in the respective lowest-order positions in the lower order rows of addition circuits being connected to a corresponding one of said output terminals, and the lowest order output terminal being connected to the output of the partial product generator in the lowest-order position in the lowest order row of the partial product generators.
Claim 2
Dependent Claim
971 words
A binary multiplier circuit for multiplying together a multiplier and a multiplicand, the respective digits of each of said multiplier and said multiplicand being represented by respective signals supplied at respectively different input terminals at respectively different times, the signal representative of the lowest order one of said digits in each of said multiplier and multiplicand being supplied at the earliest of said different times and the signals respectively representative of the successively higher-order ones of said digits being supplied at successively later times, adjacent ones of said different times being separated by one time unit, said circuit comprising: a. first means for supplying each of said multiplier-digitrepresentative signals at each of a first number of specified successive times, said first number being equal to the number of digits in said multiplicand, and adjacent ones of said specified successive times being spaced by said one time unit; b. second means for supplying each of said multiplicand-digitrepresentative signals at each of a second number of given successive times, said second number being equal to the number of digits in said multiplier, and adjacent ones of said given successive times being spaced by two of said time units; c. a row of partial product generators for each digit of said multiplier, each row having an order corresponding to the order of the Corresponding digit of said multiplier, each of said rows of partial product generators having a number of partial product generators equal to the number of digits in said multiplicand, each partial product generator in each of said rows having a position in that row corresponding to the order of the corresponding digit of said multiplicand, each of said partial product generators having means for receiving a first input and a second input and for producing an output; d. means coupled to said first means, for supplying, at successive times separated by one of said time units, that one of said signals which is representative of a digit of given order of said multiplier, to said first input of successive ones of said partial product generators located in that row of partial product generators corresponding to said given order; e. means coupled to said second means, for supplying, at successive times separated by two of said time units, that one of said signals which is representative of a digit of specified order of said multiplicand, to said second input of successive ones of said partial product generators located, in said rows of partial product generators, in respective positions corresponding to said specified order; f. a plurality of ordered rows of addition circuit arranged so that the lowest order row of addition circuits corresponds to the second lowest order digit of said multiplier, there being one less row of addition circuits than there are rows of partial product generators, each addition circuit in each of said rows of addition circuits having a position in that row corresponding to the order of the corresponding digit of said multiplicand, each of said addition circuits having means for receiving a first input and for providing a sum output and a carry output, each of said addition circuits except the highest order addition circuit in said lowest order row of addition circuits having means for receiving a second input, and each of said addition circuits except the addition circuit in the lowest-order position in each row of addition circuits having means for receiving a carry input; g. each of said addition circuits except the addition circuit in the lowest-order position in each of said rows of addition circuits being connected to receive a carry input from the addition circuit in the next-lower order position in said row, means for supplying to addition circuits in said lowest order row of addition circuits, as said second input, the outputs of the partial product generators of respectively corresponding position in the second lowest order row of partial product generators, and means for supplying to each addition circuit in said lowest order row of addition circuits except the addition circuit in the highest-order position in that row, as said first input, the output of the partial product generator in the next-higher-order position in the lowest order row of partial product generators; each of said addition circuits in the remaining rows of addition circuits corresponding to the third and higher order digits of said multiplier being connected to receive as a first input the output of the partial product generator in the same position in the same order row of partial product generators; all addition circuits except the addition circuit in the highest order position in each of said remaining rows of addition circuits being connected to receive as a second input the sum output of the addition circuit in the next-higher-order position in the next lower order row of addition circuits; and the order addition circuit in the highest-order position in each of the said remaining rows of addition circuits being connected to receive as a second input the carry output of the addition circuit in the highest-order position in the previous row of addition circuits; h. and a plurality of output terminals, the highest order output terminal being connected to the carry output of the addition circuit in the highest-order pOsition in the highest order row of addition circuits, each of said sum outputs of each of said addition circuits in the highest order row of addition circuits being connected to a corresponding one of said output terminals, each of said sum outputs of the addition circuits in the respective lowest-order positions in the lower order rows of addition circuits being connected to a corresponding one of said output terminals, and the lowest order output terminal being connected to the output of the partial product generator in the lowest-order position in the lowest order row of the partial product generators.
Claim 3
Dependent Claim
26 words
A binary multiplier circuit as defined in claim 1 wherein said first means and said second means respectively comprise first and second sets of shift registers.
Claim 4
Dependent Claim
118 words
A binary multiplier circuit as defined in claim 2 wherein said first set of shift registers comprises a shift register for each digit in said multiplier, each shift register in said first set of shift registers having as many sections as the sum of (a) the number of digits in said multiplicand and (b) the power of two corresponding to the order of said multiplier digit which is spaced in time by said shift register; and said second set of shift registers comprises a shift register for each digit of said multiplicand, each shift register in said second set of shift registers having as many sections as one less than twice the number of digits in said multiplier.
Claim 5
Dependent Claim
44 words
A binary multiplier circuit as defined in claim 1 wherein each said partial product generator and each said addition circuit includes storage means for holding the outputs generated by said generator and said addition circuit, respectively, for at least one of said time units.
Claim 6
Dependent Claim
26 words
A binary multiplier circuit as defined in claim 4 wherein said first means and said second means respectively comprise first and second sets of shift registers.
Claim 7
Dependent Claim
118 words
A binary multiplier circuit as defined in claim 5 wherein said first set of shift registers comprises a shift register for each digit in said multiplier, each shift register in said first set of shift registers having as many sections as the sum of (a) the number of digits in said multiplicand and (b) the power of two corresponding to the order of said multiplier digit which is spaced in time by said shift register; and said second set of shift registers comprises a shift register for each digit of said multiplicand, each shift register in said second set of shift registers having as many sections as one less than twice the number of digits in said multiplier.
Claim 8
Dependent Claim
739 words
In a binary multiplier circuit for multiplying together a multiplier and a multiplicand, each of said multiplier and multiplicand having at least a first digit and a second digit, said second digit being of the next higher order than said first digit, said digits of each of said multiplier and said multiplicand being represented by respective signals supplied at respectively different terminals at respectively different times, said signals representative of the higher order one of said digits in each of said multiplier and multiplicand being supplied one time unit later than said signals representative of the lower order one of said digits said multiplier and multiplicand, respectively, the combination comprising: a. first means for supplying said signal representative of said first digit of said multiplier at a first time, and also at a second time spaced one time unit from said first time; b. second means for supplying said signal representative of said second digit of said multiplier at a third time and also at a fourth time said third time being spaced by said one time unit from said second time, and said fourth time being spaced by said one time unit from said third time; c. third means for supplying said signal representative of said first digit of said multiplicand at said first time and also at said third time; d. fourth means for supplying said signal representative of said second digit of said multiplicand at said second time and also at said fourth time; e. a first row and a second row of partial product generators, each of said rows of partial product generators comprising a first partial product generator and a second partial product generator, each of said partial product generators having means for receiving a first input signal and a second input signal and for producing an output signal; f. means coupling said first means to the respective first inputs of said partial product generators in said first row, for supplying said signal representative of said first multiplier digit, at said first time to said first partial product generator in said first row, and at said second time to said second partial product generator in said first row; means coupling said second means to the respective first inputs of said partial product generators in said second row, for supplying said signal representative of said second multiplier digit, at said third time to said first product generator in said second row, and at said fourth time to said second product generator in said second row; means coupling said third means to the respective second inputs of said first partial product generators in said first row and said second row, for supplying said signal representative of said first multiplicand digit, at said first time to said first partial product generator in said first row, and at said third time to said first partial product generator in said second row; and means coupling said fourth means to the respective second inputs of said second partial product generators in said first row and said second row, for supplying said signal representative of said second multiplicand digits, at said second time to said second partial product generator in said first row, and at said fourth time to said second partial product generator in said second row; g. a first addition circuit having at least a first input, a second input, a sum output, and a carry output; h. a second addition circuit having at least a first input, a carry input, a carry output and a sum output; i. means for connecting said first inputs of said first addition circuit and said second addition circuit respectively to said outputs of said first partial product generator and said second partial product generator in said second row respectively, and for connecting said second input of said first addition circuit to said output of said second partial product generator in said first row, and means for connecting the carry output of said first addition circuit to said carry input of said second addition circuit; j. first, second, third, and fourth conductors; k. means for connecting said first conductors to said output of said first partial product generator in said first row, means for connecting said second conductor and said third conductor to said sum outputs of said first addition circuit and said second addition circuit respectively, and means for connecting said fourth conductor to said carry output of said second addition circuit.
Claim 9
Dependent Claim
739 words
In a binary multiplier circuit for multiplying together a multiplier and a multiplicand, each of said multiplier and multiplicand having at least a first digit and a second digit, said second digit being of the next higher order than said first digit, said digits of each of said multiplier and said multiplicand being represented by respective signals supplied at respectively different terminals at respectively different times, said signals representative of the higher order one of said digits in each of said multiplier and multiplicand being supplied one time unit later than said signals representative of the lower order one of said digits said multiplier and multiplicand, respectively, the combination comprising: a. first means for supplying said signal representative of said first digit of said multiplier at a first time, and also at a second time spaced one time unit from said first time; b. second means for supplying said signal representative of said second digit of said multiplier at a third time and also at a fourth time said third time being spaced by said one time unit from said second time, and said fourth time being spaced by said one time unit from said third time; c. third means for supplying said signal representative of said first digit of said multiplicand at said first time and also at said third time; d. fourth means for supplying said signal representative of said second digit of said multiplicand at said second time and also at said fourth time; e. a first row and a second row of partial product generators, each of said rows of partial product generators comprising a first partial product generator and a second partial product generator, each of said partial product generators having means for receiving a first input signal and a second input signal and for producing an output signal; f. means coupling said first means to the respective first inputs of said partial product generators in said first row, for supplying said signal representative of said first multiplier digit, at said first time to said first partial product generator in said first row, and at said second time to said second partial product generator in said first row; means coupling said second means to the respective first inputs of said partial product generators in said second row, for supplying said signal representative of said second multiplier digit, at said third time to said first product generator in said second row, and at said fourth time to said second product generator in said second row; means coupling said third means to the respective second inputs of said first partial product generators in said first row and said second row, for supplying said signal representative of said first multiplicand digit, at said first time to said first partial product generator in said first row, and at said third time to said first partial product generator in said second row; and means coupling said fourth means to the respective second inputs of said second partial product generators in said first row and said second row, for supplying said signal representative of said second multiplicand digits, at said second time to said second partial product generator in said first row, and at said fourth time to said second partial product generator in said second row; g. a first addition circuit having at least a first input, a second input, a sum output, and a carry output; h. a second addition circuit having at least a first input, a carry input, a carry output and a sum output; i. means for connecting said first inputs of said first addition circuit and said second addition circuit respectively to said outputs of said first partial product generator and said second partial product generator in said second row respectively, and for connecting said second input of said first addition circuit to said output of said second partial product generator in said first row, and means for connecting the carry output of said first addition circuit to said carry input of said second addition circuit; j. first, second, third, and fourth conductors; k. means for connecting said first conductors to said output of said first partial product generator in said first row, means for connecting said second conductor and said third conductor to said sum outputs of said first addition circuit and said second addition circuit respectively, and means for connecting said fourth conductor to said carry output of said second addition circuit.
Claim 10
Dependent Claim
66 words
A binary multiplier circuit according to claim 7, wherein said means for connecting said second input of said first addition circuit to said output of said second partial product generator in said first row comprises a third addition circuit having an input connected to said output of the last-named partial product generator and a sum output connected to said second input of said first addition circuit.
Claim 11
Dependent Claim
88 words
A binary multiplier circuit according to claim 8, wherein said third means for supplying at said third time said signal representative of said first multiplicand digit comprises means for inverting said signal representative of said first multiplicand digit and for supplying said inverted signal at said third time; and said fourth means for supplying at said fourth time said signal representative of said second multiplicand digit comprises means for inverting said signal representative of saiD second multiplicand digit and supplying the latter inverted signal at said fourth time.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-25 | 1977-08-27 | 1978-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-25 | 1981-08-27 | 1982-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-25 | 1985-08-27 | 1986-02-26 | $7700.00 | Window Closed / Lapsed |