Modular pipeline multiplier to generate a rounded product

Claim 1

A pipeline digital multiplier circuit for forming the rounded product of an n-bit data word and an m-bit coefficient word comprising a. m identical stages, each comprising i. first, second and third input terminals and an output terminal, ii. means for applying a uniquely associated bit of said coefficient word to said first input terminal, iii. means for forming during the ith time interval the bit product of said bit applied at said first input terminal with a data bit applied at said second input terminal, iv. means for generating a sum signal by adding said bit product to a bit representative of a partial product generated during the (i-1)th time interval and a bit representative of carry signals from previous additions, v. means for selectively inhibiting said sum signal to eliminate those sum signals which contribute only to one of the bits of the truncated portion of the product of said data word and said coefficient word, vi. means for applying said selectively inhibited sum signal to said output terminal, b. means for connecting the output terminal of each stage but the last to the third input terminal of the next succeeding stage, c. means for sequentially applying said n-bit data word to the second input terminal of the first of said stages, and d. means for applying a logic 1 signal to said means for generating a sum signal in said first stage.