Memory device and method implementing wordline redundancy without an access time penalty

Claim 2

A semiconductor memory device comprising: main wordline driver means for producing a main driver signal to be applied to a main wordline in a main memory array; redundant wordline driver means for producing a redundant driver signal to be applied to a redundant wordline in a redundant memory array; redundant word decoder means, associated with at least one redundant wordline, for comparing an input address signal with defective main memory wordline addresses and, in response to the comparison, producing at least one comparison signal to control the propagation of said redundant driver signal along said at least one redundant wordline; and main trigger means receiving said at least one comparison signal and, in response thereto, controlling a triggering of said main wordline driver means to produce said main driver signal; wherein said main trigger means and said redundant word decoder means are responsive to opposite states of said at least one comparison signal, such that, for a given comparison signal, only one of said main driver signal and redundant driver signal is allowed to propagate to said main and redundant memory array.

Claim 3

A semiconductor memory device comprising: main wordline driver means for producing a main driver signal to be applied to a main wordline in a main memory array; redundant wordline driver means for producing a redundant driver signal to be applied to a redundant wordline in a redundant memory array; redundant word decoder means, associated with at least one redundant wordline, for comparing an input address signal with defective main memory wordline addresses and, in response to the comparison, producing at least one comparison signal to control the propagation of said redundant driver signal along said at least one redundant wordline; main trigger means receiving said at least one comparison signal and, in response thereto, controlling a triggering of said main wordline driver means to produce said main driver signal; main word decoder means for performing a switching operation, in response to said input address signal, for directing the propagation of said main driver signal to said main wordline in said main memory array; redundant trigger means for controlling the triggering of said redundant wordline driver means to produce said redundant driver signal; and settling signal means for producing a settling signal to be applied to said main and redundant trigger means for controlling the triggering of said main and redundant wordline driver means, wherein said settling signal means has a construction and operation which are substantially similar to a decoder circuit of said main word decoder means such that said settling signal is not output until a time when said switching operation of said main word decoder means can be guaranteed as being settled; and wherein said main trigger means and said redundant word decoder means are responsive to opposite states of said at least one comparison signal, such that, for a given comparison signal, only one of said main driver signal and redundant driver signal is allowed to propagate to said main and redundant memory array.

Claim 4

A semiconductor memory device comprising: main wordline driver means for producing a main driver signal to be applied to a main wordline in a main memory array; redundant wordline driver means for producing a redundant driver signal to be applied to a redundant wordline in a redundant memory array; redundant word decoder means, associated with at least one redundant wordline, for comparing an input address signal with defective main memory wordline addresses and, in response to the comparison, producing at least one comparison signal to control the propagation of said redundant driver signal along said at least one redundant wordline; main trigger means receiving said at least one comparison signal and, in response thereto, controlling a triggering of said main wordline driver means to produce said main driver signal; main word decoder means for performing a switching operation, in response to said input address signal, for directing the propagation of said main driver signal to said main wordline in said main memory array; redundant trigger means for controlling the triggering of said redundant wordline driver means to produce said redundant driver signal; and settling signal means for producing a settling signal to be applied to said main and redundant trigger means for controlling the triggering of said main and redundant wordline driver means, wherein said settling signal means has a construction and operation which are substantially similar to a decoder circuit of said main word decoder means such that said settling signal is not output until a time when said switching operation of said main word decoder means can be guaranteed as being settled; and wherein said main trigger means and said redundant word decoder means are responsive to opposite states of said at least one comparison signal, such that, for a given comparison signal, only one of said main driver signal and redundant driver signal is allowed to propagate to said main and redundant memory array.

Claim 5

A semiconductor memory device as claimed in claim 2, wherein: said redundant trigger means comprises redundant charging means, the output of which controls the triggering of said redundant wordline driver means, the operation of said redundant charging means being controlled by a redundant grounding means which receives and is controlled by said settling signal; and said main trigger means comprises main charging means, the output of which controls the triggering of said main wordline driver means, the operation of said main charging means being controlled by a plurality of respective grounding means, each of which receives and is controlled by a different one of said settling signal and said at least one comparison signal.

Claim 6

A semiconductor memory device as claimed in claim 3, wherein: said at least one comparison signal is not output until a time when said switching operation of said main word decoder means can be guaranteed as being settled.

Claim 7

A semiconductor memory device as claimed in claim 4, wherein: said redundant word decoder means performs a switching operation to allow the propagation of said redundant driver signal to a redundant wordline when said input address signal corresponds to a defective address.

Claim 8

A semiconductor memory device as claimed in claim 5, wherein said redundant word decoder means is programmable with defective addresses.

Claim 9

A semiconductor memory device as claimed in claim 6, wherein said comparison signal can be output as one of a first and second state, said first state being indicative of a match between the input address signal and a defective address, said second state being indicative of a non-match between the input address signal and a defective address.

Claim 10

A semiconductor memory device comprising: main wordline driver means for producing a main driver signal to be applied to a main wordline in a main memory array; redundant wordline driver means for producing a redundant driver signal to be applied to a redundant wordline in a redundant memory array; redundant word decoder means, associated with at least one redundant wordline, for comparing an input address signal with defective main memory wordline addresses and, in response thereto, producing at least one comparison signal to control the propagation of said redundant driver signal along said at least one redundant wordline; main word decoder means for performing a switching operation, in response to said input address signal, for directing the propagation of said main driver signal to said main wordline in said main memory array; main trigger means for receiving said at least one comparison signal and, in response thereto, controlling a triggering of said main wordline driver means to produce said driver signal; redundant trigger means for controlling the triggering of said redundant wordline driver means to produce said redundant driver signal; and settling signal means for producing a settling signal to be applied to said main and redundant trigger means for controlling the triggering of said main and redundant wordline driver means, wherein said settling signal is not output until a time when said switching operation of said main word decoder means can be guaranteed as being settled; and wherein said main trigger means and said redundant word decoder means are responsive to opposite states of said at least one comparison signal, such that only one of said main driver signal and redundant driver signal is allowed to propagate to said main and redundant memory array for a given comparison signal.

Claim 11

A semiconductor memory device comprising: main wordline driver means for producing a main driver signal to be applied to a main wordline in a main memory array; redundant wordline driver means for producing a redundant driver signal to be applied to a redundant wordline in a redundant memory array; redundant word decoder means, associated with at least one redundant wordline, for comparing an input address signal with defective main memory wordline addresses and, in response thereto, producing at least one comparison signal to control the propagation of said redundant driver signal along said at least one redundant wordline; main word decoder means for performing a switching operation, in response to said input address signal, for directing the propagation of said main driver signal to said main wordline in said main memory array; main trigger means for receiving said at least one comparison signal and, in response thereto, controlling a triggering of said main wordline driver means to produce said driver signal; redundant trigger means for controlling the triggering of said redundant wordline driver means to produce said redundant driver signal; and settling signal means for producing a settling signal to be applied to said main and redundant trigger means for controlling the triggering of said main and redundant wordline driver means, wherein said settling signal is not output until a time when said switching operation of said main word decoder means can be guaranteed as being settled; and wherein said main trigger means and said redundant word decoder means are responsive to opposite states of said at least one comparison signal, such that only one of said main driver signal and redundant driver signal is allowed to propagate to said main and redundant memory array for a given comparison signal.

Claim 12

A semiconductor memory device as claimed in claim 8, wherein: said redundant trigger means comprises redundant charging means, the output of which controls the triggering of said redundant wordline driver means, the operation of said redundant charging means being controlled by a redundant grounding means which receives and is controlled by said settling signal; and said main trigger means comprises main charging means, the output of which controls the triggering of said main wordline driver means, the operation of said main charging means being controlled by a plurality of respective grounding means, each of which receives and is controlled by a different one of said settling signal and said at least one comparison signal.

Claim 13

A semiconductor memory device as claimed in claim 9, wherein said at least one comparison signal is not output until a time when said switching operation of said main word decoder means can be guaranteed as being settled.

Claim 14

A semiconductor memory device as claimed in claim 10, wherein: said redundant word decoder means performs a switching operation to allow the propagation of said redundant driver signal to a redundant wordline when said input address signal corresponds to a defective address.

Claim 15

A semiconductor memory device as claimed in claim 11, wherein said redundant word decoder means is programmable with defective addresses.

Claim 16

A semiconductor device as claimed in claim 12, wherein said comparison signal can be output as one of a first and second state, said first state being indicative of a match between the input address signal and a defective address, said second state being indicative of a non-match between the input address signal and a defective address.

Claim 21

A method as claimed in claim 15, comprising the further method step of: performing a switching operation with a redundant word decoder means to select a redundant wordline when said input address signal corresponds to a defective address.

Claim 22

A method as claimed in claim 15, wherein said comparison signal can be output as one of a first and second state, said first state being indicative of a match between the input address signal and a defective address, said second state being indicative of a non-match between the input address signal and a defective address.