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US4884267A Expired / Lapsed US ⏱️ 0.0 years remaining

TDM transmission system

Assignee: Kenwood KK
•
Filing: 1987-05-28
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Granted: 1989-11-28
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Expires: 2007-05-28
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Abstract

Abstract A time division multiplex transmission system includes: a time division multiplex encoder for supplying a master clock to a plurality of PCM digital signal sources having a same sampling frequency and a same quantization bit number to effect clock synchronization and generating a time-divisionally multiplexed data signal based on a data word not D/A converted and sampled from each digital signal source; a transmission line for transmitting the multiplexed data signal from the time division multiplex encoder; and a time division demultiplex decoder for selecting a desired transmitted, multiplexed data signal and demultiplexing the selected data signal in accordance with a transmission rate before the time division multiplexing.

Inventors

  • 👤 Yukihiko Miyamoto
  • 👤 Hirokazu Kobayashi
  • 👤 Syoichi Suzuki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 20:37
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0079; H04L7/0083; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626; H04J3/0629; H04L5/00; H04L5/22; H04L5/24; H04L5/245; H04J3/0635; H04J3/0685; H04J3/0688

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 197 words
A time division multiplex system comprising: time division multiplex transmitter means which comprises; a base timing unit for supplying a master clock to a plurality of PCM digital signal sources having a same sampling frequency and a same quantization bit number to effect frequency synchronization; a digital I/O interface unit for adjusting the phase of each sample data word not D/A converted and sampled from said digital signal source; a low order encoder unit for obtaining a low order encoder output of a predetermined format at a same timing from said base timing unit, based on said data word signal phase-adjusted by said digital I/O interface unit; and a time division multiplex unit for obtaining a time-divisionally multiplexed signal by time-divisionally multiplexing said low order encoder output in units of frame row: and time division demultiplex receiver means which comprises; a time division demultiplex unit for demultiplexing said time-divisionally multiplexed signal in units of frame row and outputting a low order signal having a predetermined format expanded in accordance with an original transmission rate; and a low order decoder unit inputted with said low order signal of a predetermined format and decoding the sampled data word signal.
Claim 2
Dependent Claim 197 words
A time division multiplex system comprising: time division multiplex transmitter means which comprises; a base timing unit for supplying a master clock to a plurality of PCM digital signal sources having a same sampling frequency and a same quantization bit number to effect frequency synchronization; a digital I/O interface unit for adjusting the phase of each sample data word not D/A converted and sampled from said digital signal source; a low order encoder unit for obtaining a low order encoder output of a predetermined format at a same timing from said base timing unit, based on said data word signal phase-adjusted by said digital I/O interface unit; and a time division multiplex unit for obtaining a time-divisionally multiplexed signal by time-divisionally multiplexing said low order encoder output in units of frame row: and time division demultiplex receiver means which comprises; a time division demultiplex unit for demultiplexing said time-divisionally multiplexed signal in units of frame row and outputting a low order signal having a predetermined format expanded in accordance with an original transmission rate; and a low order decoder unit inputted with said low order signal of a predetermined format and decoding the sampled data word signal.
Claim 3
Dependent Claim 227 words
A time division multiplex system comprising: time division multiplex transmitter means which comprises; a base timing unit for supplying a master clock to a plurality of PCM digital signal sources having a same sampling frequency and a same quantization bit number to effect frequency synchronization; a digital I/O interface unit for adjusting the phase of each sample data word not D/A converted and sampled from said digital signal source; a low order encoder unit for obtaining a low order encoder output of a predetermined format at a same timing from said base timing unit, based on said date word signal phase-adjusted by said digital I/O interface unit; a time division multiplex unit for obtaining a time-divisionally multiplexed by time-divisionally multiplexing said low order encoder output in units of frame row; and a modulator for modulating a carrier by said demultiplexed signal, outputting and transmitting said modulated demultiplexed signal; and time division demultiplex receiver means which comprises; a demodulator for demodulating said modulated carrier; a time division demultiplex unit for demultiplexing a desired multiplexed and demodulated data word signal from said demodulator in units of frame row and outputting a low order signal having a predetermined format expanded in accordance with an original transmission rate; and a low order decoder unit inputted with said low order signal of a predetermined format and decoding the sampled data word signal.
Claim 4
Dependent Claim 227 words
A time division multiplex system comprising: time division multiplex transmitter means which comprises; a base timing unit for supplying a master clock to a plurality of PCM digital signal sources having a same sampling frequency and a same quantization bit number to effect frequency synchronization; a digital I/O interface unit for adjusting the phase of each sample data word not D/A converted and sampled from said digital signal source; a low order encoder unit for obtaining a low order encoder output of a predetermined format at a same timing from said base timing unit, based on said date word signal phase-adjusted by said digital I/O interface unit; a time division multiplex unit for obtaining a time-divisionally multiplexed by time-divisionally multiplexing said low order encoder output in units of frame row; and a modulator for modulating a carrier by said demultiplexed signal, outputting and transmitting said modulated demultiplexed signal; and time division demultiplex receiver means which comprises; a demodulator for demodulating said modulated carrier; a time division demultiplex unit for demultiplexing a desired multiplexed and demodulated data word signal from said demodulator in units of frame row and outputting a low order signal having a predetermined format expanded in accordance with an original transmission rate; and a low order decoder unit inputted with said low order signal of a predetermined format and decoding the sampled data word signal.
Claim 5
Dependent Claim 43 words
A time division multiplex transmission system according to claim 2, wherein said plurality of digital signal sources are digital regenerating apparatus and a master clock commonly used by said digital regenerating apparatus in supplied from said base timing unit to effect frequency synchronization.
Claim 6
Dependent Claim 43 words
A time division multiplex transmission system according to claim 2, wherein a synchronized, PCM audio sample data word and a stereo changeover signal or a sampling frequency signal are supplied from said digital signal source to a BS format low order encoder unit.
Claim 7
Dependent Claim 42 words
A time division multiplex transmission system according to claim 2, wherein said modulator of said time division multiplex transmission means is a 4 phase DPSK modulator, and said demodulator of said time division demultiplex reception means is a 4 phase DPSK demodulator.
Claim 8
Dependent Claim 227 words
A time division multiplex transmission system comprising: a first digital data source (e.g., 7 in FIG. 7) for producing a sequence of first digital sample data words; a second digital data source (e.g., 8 in FIG. 7) for producing a sequence of second digital sample data words; a time division multiplex encoder (e.g., 3 in FIG. 7) for time-division multiplexing the first and second digital sample data words into a time division multiplexed signal; wherein said time division multiplex encoder in response to the sampling rate in said first digital data source generates master clock and transmission clock, and said second digital data source in synchronization with the master clock produces the sequence of second digital sample data words, a modulator (e.g., 4 in FIG. 7) for modulating the time-division multiplexed signal with the transmission clock generated by said time division multiplex encoder and transmitting the modulated time-division multiplexed signal; a demodulator for demodulating the transmitted modulated time-division multiplexed signal; a transmission rate discriminator (e.g., 6 in FIG. 7) in response to the demodulated time-division multiplexed signal for identifying the transmission rate as one among preselected different frequency domains which are respectively assigned to a plurality of narrow band phase locked loop circuits, the identified one of which plays to generate the demultiplexing clock; a time division de-multiplex decoder for time-division de-multiplexing the transmitted time-division multiplexed signal.
Claim 9
Dependent Claim 227 words
A time division multiplex transmission system comprising: a first digital data source (e.g., 7 in FIG. 7) for producing a sequence of first digital sample data words; a second digital data source (e.g., 8 in FIG. 7) for producing a sequence of second digital sample data words; a time division multiplex encoder (e.g., 3 in FIG. 7) for time-division multiplexing the first and second digital sample data words into a time division multiplexed signal; wherein said time division multiplex encoder in response to the sampling rate in said first digital data source generates master clock and transmission clock, and said second digital data source in synchronization with the master clock produces the sequence of second digital sample data words, a modulator (e.g., 4 in FIG. 7) for modulating the time-division multiplexed signal with the transmission clock generated by said time division multiplex encoder and transmitting the modulated time-division multiplexed signal; a demodulator for demodulating the transmitted modulated time-division multiplexed signal; a transmission rate discriminator (e.g., 6 in FIG. 7) in response to the demodulated time-division multiplexed signal for identifying the transmission rate as one among preselected different frequency domains which are respectively assigned to a plurality of narrow band phase locked loop circuits, the identified one of which plays to generate the demultiplexing clock; a time division de-multiplex decoder for time-division de-multiplexing the transmitted time-division multiplexed signal.
Claim 10
Dependent Claim 32 words
A time division multiplex transmission system according to claim 6, wherein said first digital data source is a satellite broadcasting signal receiver and the sampling rate is regenerated from the received signal.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-11-27 1993-05-29 1993-11-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-11-27 1997-05-29 1997-11-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-11-27 2001-05-29 2001-11-28 $7700.00 Window Closed / Lapsed

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