US4884232A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Parallel processing circuits for high speed calculation of the dot product of large dimensional vectors
Assignee: Raytheon Co
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Filing: 1987-12-14
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Granted: 1989-11-28
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Expires: 2007-12-14
Abstract
Abstract A digital circuit executes a parallel algorithm to compute the dot product of large dimensional vectors at very high speed. The circuit may be made of a plurality of cascaded 1-bit correlator chips and a plurality of ALU chips that sum the output of the correlator chips. Alternatively, a general purpose computer architecture for implementing the invention is also provided.
Inventors
- 👤 Richard S. Schlunt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:31
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/5443; G06F17/00; G06F17/10; G06F17/16
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
209 words
A circuit for calculating a(i)·b(j) where a(i) is the vector (a,(i), a 2 (i) . . . ,a Q (i)),b(j) is the vector (b,(j),b 2 (j), . . . b Q (j)), each a k (i) is a zero or a one, and each b k (j) is a zero or a one, comprising: first memory means for storing digital signals representing a(i); second memory means for storing digital signals representing b(j); a first serial-in-parallel-out barrel shift register for creating the bit planes a(o), . . . ,a(N-1) from the digital signals stored in the first memory means; a second serial-in-parallel-out barrel shift register for creating the bit planes b(o), . . . ,b(N-1) from the digital signals stored in the second memory means; a first OR gate having a first input connected to the first serial-in-parallel-out barrel shift register; a second OR gate having a first input connected to the second serial-in-parallel-out barrel shift register; means for applying a zero or a one to a second input of each of the OR gates; a correlator connected to an output of the first OR gate and an output of the second OR gate; and mean connected to the correlator for summing a plurality of successive outputs of the correlator.
Claim 2
Dependent Claim
209 words
A circuit for calculating a(i)·b(j) where a(i) is the vector (a,(i), a 2 (i) . . . ,a Q (i)),b(j) is the vector (b,(j),b 2 (j), . . . b Q (j)), each a k (i) is a zero or a one, and each b k (j) is a zero or a one, comprising: first memory means for storing digital signals representing a(i); second memory means for storing digital signals representing b(j); a first serial-in-parallel-out barrel shift register for creating the bit planes a(o), . . . ,a(N-1) from the digital signals stored in the first memory means; a second serial-in-parallel-out barrel shift register for creating the bit planes b(o), . . . ,b(N-1) from the digital signals stored in the second memory means; a first OR gate having a first input connected to the first serial-in-parallel-out barrel shift register; a second OR gate having a first input connected to the second serial-in-parallel-out barrel shift register; means for applying a zero or a one to a second input of each of the OR gates; a correlator connected to an output of the first OR gate and an output of the second OR gate; and mean connected to the correlator for summing a plurality of successive outputs of the correlator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-27 | 1993-05-29 | 1993-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-27 | 1997-05-29 | 1997-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-27 | 2001-05-29 | 2001-11-28 | $7700.00 | Window Closed / Lapsed |