US4646327A
Expired / Lapsed
US
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Waveform shaping apparatus
Assignee: Sony Corp
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Filing: 1985-08-02
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Granted: 1987-02-24
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Expires: 2005-08-02
Abstract
Abstract A waveform shaping apparatus includes a shift register having a clock input terminal, data input terminals supplied with respective bits of a digital input signal and a plurality of data output terminals, and a plurality of coefficient multipliers connected to the respective data output terminals. A 2's-complement binary code offset within a predetermined range is used for representing the coefficient of each of the multipliers and such coefficient is controlled by manipulation of ON/OFF switches.
Inventors
- 👤 Yuichi Kojima
- 👤 Etsumi Fujita
- 👤 Yasuhiro Hideshima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 02:27
CPC Classifications
H; H04; H04B; H04B3/00; H04B3/02; H04B3/04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03114; H04L25/03133
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
115 words
A waveform shaping apparatus comprising: a shift register having a clock input terminal, a data input terminal and a plurality of data output terminals; a plurality of coefficient multipliers having respective input and output terminals, said input terminals of the coefficient multipliers being connected to respective data output terminals of said shift register, each of said coefficient multipliers using a 2's-complement binary code offset within a predetermined range from a normal 2's-complement binary code; adder means supplied with output signals from said output terminals of said coefficient multipliers to produce a summing output; and code converter means receiving said summing output for converting the same to a natural binary code or a 2's-complement binary code.
Claim 2
Dependent Claim
115 words
A waveform shaping apparatus comprising: a shift register having a clock input terminal, a data input terminal and a plurality of data output terminals; a plurality of coefficient multipliers having respective input and output terminals, said input terminals of the coefficient multipliers being connected to respective data output terminals of said shift register, each of said coefficient multipliers using a 2's-complement binary code offset within a predetermined range from a normal 2's-complement binary code; adder means supplied with output signals from said output terminals of said coefficient multipliers to produce a summing output; and code converter means receiving said summing output for converting the same to a natural binary code or a 2's-complement binary code.
Claim 3
Dependent Claim
18 words
A waveform shaping apparatus according to claim 1; in which each of said coefficient multipliers is presettable manually.
Claim 4
Dependent Claim
107 words
A waveform shaping apparatus according to claim 2; in which each of said coefficient multipliers comprises: a plurality of AND gate circuits each having first and second input terminals and an output terminal, each of said first input terminals being connected to a respective one of said data output terminals of said shift register and each said output terminal of an AND gate circuit being connected to the input of said adder means; a plurality of ON/OFF switches connected between the second input terminals of respective ones of said AND gate circuits and a reference point; and a biasing voltage source connected to said second input terminals.
Claim 5
Dependent Claim
31 words
A waveform shaping apparatus according to claim 2; further including a D/A (digital-to-analog) converter connected to said code converter means to produce an analog signal in response to said digital signal.
Claim 6
Dependent Claim
28 words
A waveform shaping apparatus according to claim 4; in which said analog signal is amplitude-modulated on a carrier and the amplitude-modulated signal is transmitted by a transmission line.
Claim 7
Dependent Claim
41 words
A waveform shaping apparatus according to claim 5; further comprising: receiving means for receiving said amplitude-modulated signal; detecting means for detecting said amplitude-modulated signal; and slicer means connected to said detecting means for demodulating said digital signal from said analog signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-23 | 1990-08-25 | 1991-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-23 | 1994-08-25 | 1995-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-23 | 1998-08-25 | 1999-02-24 | $7700.00 | Window Closed / Lapsed |