Multiplier accumulator

Claim 2

A multiplier-accumulator for accumulating a sum of products of n-bit operands S = Σ A i B i in which A i B i are successively calculated and added to the sum of the preceding products comprising: input means for holding a multiplier A i and a multiplicand B i of a product to be accumulated; multiplying means responsive to said input means for providing the partial products of multiplicand B i by each bit in the multiplier; accumulating means containing 2n adding positions, and in which the contents of each position can be provided to the next adjacent position, the contents of the last position being provided to the first position; and diverting means connected between said multiplying means and said accumulating means for transferring partial products of A i B i to a predetermined n of said adding positions, and transferring partial products of A i+1 B i+1 to the other n of said adding positions.

Claim 3

A multiplier-accumulator for accumulating an algebraic sum of products of n-bit operands S = Σ ± A i B i in which ± A i B i are successively calculated and algebraically accumulated, comprising: input means for providing a multiplier A i and a multiplicand B i of a product to be accumulated; multiplying means responsive to said input means for providing the partial products of multiplicand B i by each bit in the multiplier; accumulating means comprising a first group of n positions and a second group of n positions, wherein the contents of each position in each group can be provided to the next adjacent position in the group and the contents of the last position in each group can be provided to the first position in the other group; and diverting means having inputs connected to receive partial products from said multiplying means, and having outputs selectively connected to each of said groups of said accumulating means for providing successive sets of partial products alternately to said first group of n positions and to said second group of n positions for accumulation each set of partial products comprising all the partial products of a given term A i B i .

Claim 4

A multiplier-accumulator for accumulating an algebraic sum of products of n-bit operands S = Σ ± A i B i in which ± A i B i are successively calculated and algebraically accumulated, comprising: input means for providing a multiplier A i and a multiplicand B i of a product to be accumulated; multiplying means responsive to said input means for providing the partial products of multiplicand B i by each bit in the multiplier; accumulating means comprising a first group of n positions and a second group of n positions, wherein the contents of each position in each group can be provided to the next adjacent position in the group and the contents of the last position in each group can be provided to the first position in the other group; and diverting means having inputs connected to receive partial products from said multiplying means, and having outputs selectively connected to each of said groups of said accumulating means for providing successive sets of partial products alternately to said first group of n positions and to said second group of n positions for accumulation each set of partial products comprising all the partial products of a given term A i B i .

Claim 5

The multiplier-accumulator of claim 2 wherein: each of said positions of said accumulating means has at least two inputs and a sum output, a first input being connected to said diverting means for receiving a bit of a partial product, and the sum output being connected to the second input of the next adjacent position, said sum output providing a signal representing the algebraic sum of the input signals.

Claim 6

The multiplier-accumulator of claim 3 wherein: each of said positions also has a carry output and a carry input, said carry output being connected through a delay to said carry input.

Claim 7

The multiplier-accumulator of claim 4, particularly adapted for use in a system wherein negative numbers are expressed in complement form, further including: means connected between said input means and said accumulating means for selectively complementing A i or B i or both, in dependence upon the signs of A i and B i .

Claim 8

The multiplier-accumulator of claim 4, particularly adapted for use in a system wherein negative numbers are expressed in complement form, further including: first signalling means for providing a first signal indicating whether or not A i is in complement form; first complementing means connected in the data path between said input means and said accumulating means for complementing A i in response to said first signal indicating that A i is in complement form; second signalling means for providing a second signal when A i is in true form and the product A i B i is to be subtracted from a previous accumulation, or when A i is in complement form and the product A i B i is to be added to a previous accumulation; and second complementing means connected in the data path between said input means and said accumulating means for complementing B i in response to the presence of said second signal.

Claim 9

The multiplier-accumulator of claim 6 wherein, within each group of positions of said accumulating means: the most numerically significant position comprises means for producing a sum output and a carry output in response to first, second and carry inputs in accordance with the following truth table ______________________________________ Inputs Outputs first second carry sum carry ______________________________________ 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1 ______________________________________ and each of the other positions comprises means for producing a sum output and a carry output in response to first, second and carry inputs in accordance with the following truth table ______________________________________ Inputs Outputs first second carry sum carry ______________________________________ 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 ______________________________________

Claim 10

The multiplier-accumulator of claim 7 further including: result register means connected to said accumulating means for receiving a final accumulated result; and means connected between said accumulating means and said result register means for inverting one bit from said accumulating means.