US4884117A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit containing integrated bipolar and complementary MOS transistors on a common substrate
Assignee: Siemens AG
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Filing: 1989-03-15
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Granted: 1989-11-28
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Expires: 2009-03-15
Abstract
Abstract A circuit which contains integrated bipolar and complementary MOS transistors, including wells in the substrate for forming the MOS transistors, the wells also containing isolated bipolar transistors, the wells forming the collector of the bipolar transistor and being surrounded by trenches which are filled with doped polycrystalline silicon. The doped trench reduces the lateral out diffusion from the wells and thus serves to increase the packing density while serving as a collector contact region. The invention is employed in the manufacture of integrated semiconductor circuits having high switching speeds.
Inventors
- 👤 Franz Neppl
- 👤 Josef Winnerl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:30
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
135 words
An integrated transistor circuit, comprising: (a) a doped semiconductor substrate; (b) wells of a conductivity type opposite to that of said substrate formed in said substrate , at least one of said wells containing an MOS transistor, at least one other of said wells containing a bipolar transistor, each well containing a bipolar transistor being the collector of said transistor; and (c) trenches in said substrate surrounding said MOS and bipolar transistors such that each transistor is surrounded in its respective well by said trenches, said trenches having a filler of polycrystalline silicon of the same conductivity type but having a higher doping strength than said wells, said trenches serving to insulate between wells, the filler in the trenches surrounding each bipolar transistor forming a contact terminal for the collector of the bipolar transistor .
Claim 2
Dependent Claim
135 words
An integrated transistor circuit, comprising: (a) a doped semiconductor substrate; (b) wells of a conductivity type opposite to that of said substrate formed in said substrate , at least one of said wells containing an MOS transistor, at least one other of said wells containing a bipolar transistor, each well containing a bipolar transistor being the collector of said transistor; and (c) trenches in said substrate surrounding said MOS and bipolar transistors such that each transistor is surrounded in its respective well by said trenches, said trenches having a filler of polycrystalline silicon of the same conductivity type but having a higher doping strength than said wells, said trenches serving to insulate between wells, the filler in the trenches surrounding each bipolar transistor forming a contact terminal for the collector of the bipolar transistor .
Claim 3
Dependent Claim
21 words
An integrated circuit according to claim 1 which includes an insulating layer between the sidewalls of said trenches and said filler.
Claim 4
Dependent Claim
18 words
An integrated circuit according to claim 2 wherein said insulating layer is composed of an oxide of silicon.
References Cited (Backward Citations)
FR57126E
Cited
US3913124A
Cited
US4454647A
Cited
EP0139266A2
Cited
US4571817A
Cited
US4604790A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-27 | 1993-05-29 | 1993-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-27 | 1997-05-29 | 1997-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-27 | 2001-05-29 | 2001-11-28 | $7700.00 | Window Closed / Lapsed |