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Patent US4883978A successfully refreshed from Google Patents.
US4883978A
Expired / Lapsed
US
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Semiconductor device having reduced potential fluctuations
Assignee: Toshiba Corp
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Filing: 1988-03-11
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Granted: 1989-11-28
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Expires: 2008-03-11
Abstract
Abstract For a semiconductor integrated circuit having a data output buffer, separate power source pads and separate reference pads are provided for the data output buffer and the circuit components. Thus, any potential fluctuations or noise generated in the data output buffer are not transmitted to the circuit components, resulting in decreased circuit malfunction.
Inventors
- 👤 Shigeo Ohshima
- 👤 Hiroshi Sahara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:19
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; H; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/162; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
185 words
A semiconductor device including a semiconductor integrated circuit having a plurality of circuit components, said device comprising: first and second power source pads coupled to the high potential side of an external power source by means of respective wirings; first and second reference pads coupled to the reference potential side of said external power source by means of respective wirings; a data output buffer having a data output terminal comprising first and second transistors coupled in series between the first power source pad and the first reference pad for supplying an output signal in response to a signal supplied by the semiconductor integrated circuit; and first and second gate circuits, each gate circuit associated with a respective one of said first and second series connected transistors for generating a signal to control the switching of the corresponding transistor, said gate circuits being circuit components of said semiconductor integrated circuit, said first gate circuit coupled between said second power source pad and said first reference pad, said second gate circuit and remaining circuit components coupled between said second power source pad and said second reference pad.
Claim 2
Dependent Claim
185 words
A semiconductor device including a semiconductor integrated circuit having a plurality of circuit components, said device comprising: first and second power source pads coupled to the high potential side of an external power source by means of respective wirings; first and second reference pads coupled to the reference potential side of said external power source by means of respective wirings; a data output buffer having a data output terminal comprising first and second transistors coupled in series between the first power source pad and the first reference pad for supplying an output signal in response to a signal supplied by the semiconductor integrated circuit; and first and second gate circuits, each gate circuit associated with a respective one of said first and second series connected transistors for generating a signal to control the switching of the corresponding transistor, said gate circuits being circuit components of said semiconductor integrated circuit, said first gate circuit coupled between said second power source pad and said first reference pad, said second gate circuit and remaining circuit components coupled between said second power source pad and said second reference pad.
Claim 3
Dependent Claim
42 words
The semiconductor device according to claim 1 wherein said first series-connected transistor is coupled between the first power source pad and the data output terminal and said second series-connected transistors is coupled between the first reference pad and the data output terminal.
Claim 4
Dependent Claim
152 words
A semiconductor device including a semiconductor integrated circuit having a plurality of circuit components coupled to a common power source along the same first and second current paths, said device comprising: a data output buffer having a data output terminal comprising first and second switches coupled to the common power source along third and fourth current paths for supplying an output signal in response to a signal supplied by the semiconductor integrated circuit; first and second switch control circuits, each switch control circuit associated with a respective one of said first and second switches for generating a signal to control the switching of the corresponding switch, said first switch control means coupled to said power source along said first and second paths and said second switch control means coupled to said power source along said first and fourth paths, said first and second paths being independent of said third and fourth paths.
Claim 5
Dependent Claim
152 words
A semiconductor device including a semiconductor integrated circuit having a plurality of circuit components coupled to a common power source along the same first and second current paths, said device comprising: a data output buffer having a data output terminal comprising first and second switches coupled to the common power source along third and fourth current paths for supplying an output signal in response to a signal supplied by the semiconductor integrated circuit; first and second switch control circuits, each switch control circuit associated with a respective one of said first and second switches for generating a signal to control the switching of the corresponding switch, said first switch control means coupled to said power source along said first and second paths and said second switch control means coupled to said power source along said first and fourth paths, said first and second paths being independent of said third and fourth paths.
Claim 6
Dependent Claim
23 words
The semiconductor device according to claim 3 wherein said first and second switches comprise a first and a second transistor connected in series.
Claim 7
Dependent Claim
21 words
The semiconductor device according to claim 3 wherein said first and second switches control circuits comprise first and second gate circuits.
Claim 8
Dependent Claim
21 words
The semiconductor device according to claim 3 wherein said semiconductor integrated circuit comprises a memory having a multi-bit data output system.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-27 | 1993-05-29 | 1993-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-27 | 1997-05-29 | 1997-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-27 | 2001-05-29 | 2001-11-28 | $7700.00 | Window Closed / Lapsed |