US4883772A — Process for making a self-aligned silicide shunt

Claim 1

Independent Claim 240 words

A process for fabricating a low resistance shunt for a silicon semiconductor structure comprising: on a layer of first conductivity type silicon semiconductor material having a surface, forming a masking region over a first portion of the surface but not over a second portion; oxidizing the second portion to form an insulating region of oxidized silicon semiconductor material to separate at the surface the first portion of the layer from the second portion, the insulating region encroaching beneath the masking region to thereby reduce the size of the first portion; in predetermined order (a) removing the masking region and (b) introducing opposite conductivity type impurity into the first portion to thereby form a first region; subsequently forming a first electrical connection to the first region, which connection extends at least over the part of the insulating region which was encroaching beneath the masking region; forming a second electrical connection over the layer of first conductivity type semiconductor material, which second electrical connection is spaced apart from the first electrical connection; using the first and second electrical connections as a mask, removing a part of the insulating region to expose the surface of the first conductivity layer while leaving at least that portion of the insulating layer encroaching beneath the masking region; and depositing a silicide-forming metal onto at least the surface of the layer to form a low resistance shunt of metal silicide between said first and second electrical connections.

Claim 2

Dependent Claim 240 words

A process for fabricating a low resistance shunt for a silicon semiconductor structure comprising: on a layer of first conductivity type silicon semiconductor material having a surface, forming a masking region over a first portion of the surface but not over a second portion; oxidizing the second portion to form an insulating region of oxidized silicon semiconductor material to separate at the surface the first portion of the layer from the second portion, the insulating region encroaching beneath the masking region to thereby reduce the size of the first portion; in predetermined order (a) removing the masking region and (b) introducing opposite conductivity type impurity into the first portion to thereby form a first region; subsequently forming a first electrical connection to the first region, which connection extends at least over the part of the insulating region which was encroaching beneath the masking region; forming a second electrical connection over the layer of first conductivity type semiconductor material, which second electrical connection is spaced apart from the first electrical connection; using the first and second electrical connections as a mask, removing a part of the insulating region to expose the surface of the first conductivity layer while leaving at least that portion of the insulating layer encroaching beneath the masking region; and depositing a silicide-forming metal onto at least the surface of the layer to form a low resistance shunt of metal silicide between said first and second electrical connections.

Claim 3

Dependent Claim 13 words

A process as in claim 1 wherein the first electrical connection comprises aluminum.

Claim 4

Dependent Claim 12 words

A process as in claim 2 wherein the silicide-forming metal comprises copper.

Claim 5

Dependent Claim 12 words

A process as in claim 2 wherein the silicide-forming metal comprises nickel.

Claim 6

Dependent Claim 14 words

A process as in claim 1 wherein the first electrical connection comprises polycrystalline silicon.

Claim 7

Dependent Claim 26 words

A process as in claim 1 whereinthe step of removing a part of the insulating region comprises etching the insulating region with a fluorine containing plasma.

Claim 8

Dependent Claim 26 words

A process as in claim 1 wherein the opposite conductivity type impurity comprises N conductivity type and the doped region comprises an emitter of a transistor.

Claim 9

Dependent Claim 31 words

A process as in claim 1 wherein the step of depositing is followed by the step of heating the semiconductor structure to cause the silicide-forming metal to react with the layer.

Claim 10

Dependent Claim 32 words

A process as in claim 8 wherein the first electrical connection has a melting point and the structure is heated to a temperature below the melting point of the first electrical connection.

Claim 11

Dependent Claim 28 words

A process as in claim 9 followed by the step of removing from the structure any of the silicide-forming metal which does not react with the silicon layer.

Claim 12

Dependent Claim 23 words

A process as in claim 10 wherein the silicide-forming metal comprises nickel and the step of removing comprises etching with dilute nitric acid.

Claim 13

Dependent Claim 190 words

A process for fabricating a low resistance silicide shunt for a vertical bipolar transistor comprising: in a layer of P conductivity type silicon semiconductor material having an upper surface, forming an insulating region of oxidized silicon to separate at the surface of the layer an emitter regio from a base region; introducing N conductivity type impurity into the emitter region to thereby form an emitter; forming a first aluminum connection to the emitter, which connection extends at least over a part of the oxidized silicon; forming a second aluminum connection on the upper surface of the P conductivity type silicon semiconductor material, said second aluminum connection being spaced-apart from the first aluminum connection; using the first and second aluminum connections as a mask, plasma etching the oxidized silicon to expose the surface of the silicon layer except where protected by the aluminum connections; depositing a metal selected from the group of copper and nickel across the silicon; heating the metal to a temperature below the melting point of aluminum to thereby form the low resistance silicide shunt; and removing any of the silicide-forming metal remaining unreacted on the semiconductor structure.

Claim 14

Dependent Claim 190 words

A process for fabricating a low resistance silicide shunt for a vertical bipolar transistor comprising: in a layer of P conductivity type silicon semiconductor material having an upper surface, forming an insulating region of oxidized silicon to separate at the surface of the layer an emitter regio from a base region; introducing N conductivity type impurity into the emitter region to thereby form an emitter; forming a first aluminum connection to the emitter, which connection extends at least over a part of the oxidized silicon; forming a second aluminum connection on the upper surface of the P conductivity type silicon semiconductor material, said second aluminum connection being spaced-apart from the first aluminum connection; using the first and second aluminum connections as a mask, plasma etching the oxidized silicon to expose the surface of the silicon layer except where protected by the aluminum connections; depositing a metal selected from the group of copper and nickel across the silicon; heating the metal to a temperature below the melting point of aluminum to thereby form the low resistance silicide shunt; and removing any of the silicide-forming metal remaining unreacted on the semiconductor structure.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1992-11-27	1993-05-29	1993-11-28	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1996-11-27	1997-05-29	1997-11-28	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2000-11-27	2001-05-29	2001-11-28	$7700.00	Window Closed / Lapsed

Process for making a self-aligned silicide shunt

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