Multi-microprocessor for controlling shared memory

Claim 2

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from said terminal, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor performing its control function with respect to a respective area of said memory and a control processor responsive to a request for data from said at least one intelligent terminal for determining which one of said microprocessors is responsible for the requested data, and for forwarding said request for data to said one microprocessor.

Claim 3

A system as defined in claim 1, wherein each of said microprocessors comprises directory table means for maintaining a directory table of the data currently stored in its assigned area of said memory.

Claim 4

A system as defined in claim 1, wherein said memory comprises both a primary memory and a secondary memory with areas of said primary memory being assigned to respective ones of said plurality of microprocessors, and said control means further comprises a memory controller responsive to signals from said plurality of microprocessors for controlling transfer of data between said primary memory and secondary memory.

Claim 5

A system as defined in claim 1, wherein said memory includes at least first and second areas, wherein data can be accessed from said first area by said intelligent terminal without said data passing through said second area and wherein data can be accessed from said second area by said intelligent terminal without said data passing through said first area, and wherein said plurality of microprocessors includes at least a first microprocessor performing said at least one memory control function with respect to said first area and a second microprocessor performing said at least one memory control function with respect to said second area, said first and second microprocessors being interconnected in an array for communication between one another

Claim 6

A system as defined in claim 1, wherein said data requests from said at least one intelligent terminal identify requested data by a virtual address, with said control means performing virtual-to-real address translation and forwarding a real address of said requested data back to said intelligent terminal.

Claim 7

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from said terminal, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor normally performing its control function with respect to only a respective area of said memory, a control processor responsive to a request for data from said at least one intelligent terminal for determining which one of said microprocessors is responsible for the requested data, and for forwarding said request for data to said one microprocessor, and means for providing access by one of said microprocessors to at least a portion of the area in said memory which is normally controlled by another of said microprocessors.

Claim 8

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from said terminal, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor normally performing its control function with respect to only a respective area of said memory, a control processor responsive to a request for data from said at least one intelligent terminal for determining which one of said microprocessors is responsible for the requested data, and for forwarding said request for data to said one microprocessor, and means for providing access by one of said microprocessors to at least a portion of the area in said memory which is normally controlled by another of said microprocessors.

Claim 9

A system as defined in claim 6, wherein said data requests from said at least one intelligent terminal identify requested data by a virtual address, with said control means performing virtual-to-real address translation and forwarding a real address of said requested data back to said intelligent terminal.

Claim 10

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from said terminal, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor performing its control function with respect to a respective area of said memory and a control processor responsive to a request for data from said at least one intelligent terminal for determining which one of said microprocessors is responsible for the requested data, and for forwarding said request for data to said one microprocessor.

Claim 11

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from said terminal, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor performing its control function with respect to a respective area of said memory and a control processor responsive to a request for data from said at least one intelligent terminal for determining which one of said microprocessors is responsible for the requested data, and for forwarding said request for data to said one microprocessor.

Claim 12

A system as defined in claim 8, including at least first and second intelligent terminals, said control processor being responsive to data requests from each of said first and second intelligent terminals for determining which microprocessor is responsible for the requested data and for forwarding each request for data to the responsible microprocessor.

Claim 13

A system as defined in claim 8, wherein said data requests from said at least one intelligent terminal identify requested data by a virtual address, with said control means performing virtual-to-real address translation and forwarding a real address of said requested data back to said intelligent terminal.

Claim 14

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from said terminal, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor performing its control function with respect to a respective area of said memory and a control processor responsive to a request for data from said at least one intelligent terminal for broadcasting said request to a plurality of said microprocessors, whereby one of said microprocessors will respond to said broadcast data request.

Claim 15

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from said terminal, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor performing its control function with respect to a respective area of said memory and a control processor responsive to a request for data from said at least one intelligent terminal for broadcasting said request to a plurality of said microprocessors, whereby one of said microprocessors will respond to said broadcast data request.

Claim 16

A system as defined in claim 11, including at least first and second intelligent terminals, said control processor being responsive to data requests from each of said first and second intelligent terminals for broadcasting each request for data to said plurality of said microprocessors.

Claim 17

A system as defined in claim 11, wherein said data requests from said at least one intelligent terminal identify requested data by a virtual address, with said control means performing virtual-to-real address translation and forwarding a real address of said requested data back to said intelligent terminal.

Claim 18

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from at least one of said terminals, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor performing its control function with respect to a respective area of said memory and a control processor responsive to a request for data from said at least one intelligent terminal for determining which one of said microprocessors is responsible for the requested data, and for forwarding said request for data to said one microprocessor, said system further comprising switching means for selectively establishing connections between said intelligent terminals and said control means.

Claim 19

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from at least one of said terminals, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor performing its control function with respect to a respective area of said memory and a control processor responsive to a request for data from said at least one intelligent terminal for determining which one of said microprocessors is responsible for the requested data, and for forwarding said request for data to said one microprocessor, said system further comprising switching means for selectively establishing connections between said intelligent terminals and said control means.

Claim 20

A system as defined in claim 14, wherein said switch means further selectively establishes connections between said intelligent terminals and said memory.

Claim 21

A system as defined in claim 14, wherein said data requests from said at least one intelligent terminal identify requested data by a virtual address, with said control means performing virtual-to-real address translation and forwarding a real address of said requested data back to said at least one intelligent terminal.

Claim 22

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from at least one of said terminals, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor performing its control function with respect to a respective area of said memory and each generating a control signal for controlling transfer of data to and from its respective area of said memory, said memory comprising both a primary and a secondary memory with areas of said primary memory being assigned to respective ones of said plurality of microprocessors, and said control means further comprising a control processor responsive to a request for data from at least one of said intelligent terminals for determining which one of said microprocessors is responsible for the requested data, and for forwarding said data request to said one microprocessor and for forwarding said control signals from said processors, and a memory controller responsive to said control signals from said plurality of microprocessors via said control processor for controlling transfer of data between said primary and secondary memories, said system further comprising switch means for selectively establishing connections between said intelligent terminals and said control processor.

Claim 23

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from at least one of said terminals, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor performing its control function with respect to a respective area of said memory and each generating a control signal for controlling transfer of data to and from its respective area of said memory, said memory comprising both a primary and a secondary memory with areas of said primary memory being assigned to respective ones of said plurality of microprocessors, and said control means further comprising a control processor responsive to a request for data from at least one of said intelligent terminals for determining which one of said microprocessors is responsible for the requested data, and for forwarding said data request to said one microprocessor and for forwarding said control signals from said processors, and a memory controller responsive to said control signals from said plurality of microprocessors via said control processor for controlling transfer of data between said primary and secondary memories, said system further comprising switch means for selectively establishing connections between said intelligent terminals and said control processor.

Claim 24

A system as defined in claim 17, wherein said switch means further selectively establishes connections between said intelligent terminals and said primary memory.

Claim 25

A system as defined in claim 18, further comprising means for establishing connection for signals between said control processor and said memory controller without passing through said switch means.

Claim 26

A system as defined in claim 19, wherein said switch means further selectively establishes connection between said control processor and said memory controller.

Claim 27

A system as defined in claim 17, wherein said switch means further selectively establishes connection between said memory controller and said primary memory.

Claim 28

A system as defined in claim 17, wherein said data requests from said at least one intelligent terminal identify requested data by a virtual address, with said control means performing virtual-to-real address translation and forwarding a real address of said requested data back to said at least one intelligent terminal.

Claim 29

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from said terminal, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor normally performing its control function with respect to only a respective area of said memory, a control processor responsive to a request for data from said at least one intelligent terminal for broadcasting said request to a plurality of said microprocessors, whereby one of said microprocessors will respond to said broadcast data request, and means for providing access by one of said microprocessors to at least a portion of the area in said memory which is normally controlled by another of said microprocessors.

Claim 30

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from said terminal, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor normally performing its control function with respect to only a respective area of said memory, a control processor responsive to a request for data from said at least one intelligent terminal for broadcasting said request to a plurality of said microprocessors, whereby one of said microprocessors will respond to said broadcast data request, and means for providing access by one of said microprocessors to at least a portion of the area in said memory which is normally controlled by another of said microprocessors.

Claim 31

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from at least one of said terminals, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor performing its control function with respect to a respective area of said memory and a control processor responsive to a request for data from said at least one intelligent terminal for broadcasting said request to a plurality of said microprocessors, whereby one of said microprocessors will respond to said broadcast data request, said system further comprising switching means for selectively establishing connections between said intelligent terminals and said control means.

Claim 32

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from at least one of said terminals, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor performing its control function with respect to a respective area of said memory and a control processor responsive to a request for data from said at least one intelligent terminal for broadcasting said request to a plurality of said microprocessors, whereby one of said microprocessors will respond to said broadcast data request, said system further comprising switching means for selectively establishing connections between said intelligent terminals and said control means.

Claim 33

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from at least one of said terminals, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor performing its control function with respect to a respective area of said memory and each generating a control signal for controlling transfer of data to and from its respective area of said memory, said memory comprising both a primary and a secondary memory with areas of said primary memory being assigned to respective ones of said plurality of microprocessors, and said control means further comprising a control processor responsive to a request for data from at least one of said intelligent terminals for broadcasting said request to a plurality of said microprocessors, whereby one of said microprocessors will respond to said broadcast data request, and for forwarding said control signals from said processors, and a memory controller responsive to said control signals from said plurality of microprocessors via said control processor for controlling transfer of data between said primary and secondary memories, said system further comprising switch means for selectively establishing connections between said intelligent terminals and said control processor.

Claim 34

A data processing system of the type including at least one intelligent terminal, a memory for storing data and control means for performing at least one memory control function in accordance with data requests from at least one of said terminals, said control means comprising a plurality of microprocessors for performing said at least one memory control function in accordance with said data requests and interconnected in an array for communication between one another, each microprocessor performing its control function with respect to a respective area of said memory and each generating a control signal for controlling transfer of data to and from its respective area of said memory, said memory comprising both a primary and a secondary memory with areas of said primary memory being assigned to respective ones of said plurality of microprocessors, and said control means further comprising a control processor responsive to a request for data from at least one of said intelligent terminals for broadcasting said request to a plurality of said microprocessors, whereby one of said microprocessors will respond to said broadcast data request, and for forwarding said control signals from said processors, and a memory controller responsive to said control signals from said plurality of microprocessors via said control processor for controlling transfer of data between said primary and secondary memories, said system further comprising switch means for selectively establishing connections between said intelligent terminals and said control processor.