Cache/disk subsystem

Claim 2

A data processing system comprising: a disk drive device for driving a data storage disk; a host processor for issuing commands defining an operation to be performed and the address of disk space at which said operation is to be performed, said address specifying the starting address and a number of words of said disk space; a cache store for storing segments of data; means for storing a segment descriptor table, said segment descriptor table having an entry corresponding to each segment of data residing in said cache store; a storage control unit interfacing with said host processor, said disk drive device, said means for storing a segment descriptor table and said cache store; means in said storage control unit responsive to a command from said host processor calling for a read from said disk for accessing said segment descriptor table to produce a miss signal if a copy of the data from the disk space specified by said command is not resident in said cache store; means responsive to said miss signal for transferring from said disk space to said cache store the data from the specified disk space which is not resident in said cache store; and means in said storage control unit for controlling the transfer of the data at said specified disk space to said host processor; whereby said host processor may read from said disk any variable number of words of data as specified by said address.

Claim 3

A data processing system as claimed in claim 1 and further including at least one additional disk drive device connected to said storage control unit.

Claim 4

A data processing system as claimed in claim 2 and further including at least one additional host processor connected to said storage control unit.

Claim 5

A data processing system as claimed in claim 1 and further including at least one additional host processor, at least one additional disk drive device, and a further storage control unit interfacing said cache store, said means for storing a segment descriptor table, said additional host processor, and said additional disk drive device, whereby all of said host processors share a single cache store.

Claim 6

A data processing system as claimed in claim 4 and including means connecting said disk drive device and said additional disk drive device to both said storage control unit and said additional storage control unit.

Claim 7

A data processing system as claimed in claim 5 and including means connecting said additional host processor to said storage control unit and said additional storage control unit.

Claim 8

A data processing system as claimed in claim 1 wherein said storage control unit includes means responsive to a write command from said host processor calling for a write operation onto said disk for accessing said segment descriptor table to produce a miss signal if a copy of the data from the disk space specified by said write command is not resident in said cache store; means responsive to said miss signal for transferring from said disk space to said cache store the data from the specified disk space which is not resident in said cache store; and means in said storage control unit for writing data from said host processor into said cache store.

Claim 9

In a data processing system wherein at least one host processor issues commands including function and data addressing information to at least one storage control unit for reading data from or transferring data to at least one disk drive device attached to the storage control unit, the improvement comprising: a cache store for storing segments of data; means storing a segment descriptor table, said segment descriptor table having an entry corresponding to each segment of data residing in said cache store; control means including first means responsive to a command from a host processor calling for a read or a write from or to a disk for accessing said segment descriptor table to produce a hit signal if the segment or segments containing the data specified by said addressing information resides in said cache store, or a miss signal if it does not; means responsive to said hit signal for transferring the addressed data between said cache store and said host processor through said storage control unit; means responsive to said miss signal and said addressing information for transferring said addressed data between said disk drive and said host processor through said storage control unit with a copy thereof being entered into said cache store; said addressing information including the address of a disk drive, a relative word address defining the location on a disk of the first word to be transferred, and the number of words to be transferred, and, said first means including means for converting said disk drive address, said relative word address and said word transfer length into addressing signals for addressing said cache store.

Claim 10

In a data processing system wherein at least one host processor issues commands including function and data addressing information to at least one storage control unit for reading data from or transferring data to at least one disk drive device attached to the storage control unit, the improvement comprising: a cache store for storing segments of data; means storing a segment descriptor table, said segment descriptor table having an entry corresponding to each segment of data residing in said cache store; control means including first means responsive to a command from a host processor calling for a read or a write from or to a disk for accessing said segment descriptor table to produce a hit signal if the segment or segments containing the data specified by said addressing information resides in said cache store, or a miss signal if it does not; means responsive to said hit signal for transferring the addressed data between said cache store and said host processor through said storage control unit; means responsive to said miss signal and said addressing information for transferring said addressed data between said disk drive and said host processor through said storage control unit with a copy thereof being entered into said cache store; said addressing information including the address of a disk drive, a relative word address defining the location on a disk of the first word to be transferred, and the number of words to be transferred, and, said first means including means for converting said disk drive address, said relative word address and said word transfer length into addressing signals for addressing said cache store.

Claim 11

In a data processing system wherein a plurality of host processors issue commands including function and data addressing information to a storage control unit for reading data from or transferring data to at least one disk drive device attached to the storage control unit, the improvement comprising: a cache store for storing segments of data; means storing a segment descriptor table, said segment descriptor table having an entry corresponding to each segment of data residing in said cache store; control means including first means responsive to a command from a host processor calling for a read or a write from or to a disk for accessing said segment descriptor table to produce a hit signal if the segment or segments containing the data specified by said addressing information resides in said cache store, or a miss signal if it does not; means responsive to said hit signal for transferring the addressed data between said cache store and said host processor through said storage control unit; means responsive to said miss signal and said addressing information for transferring said addressed data between said disk drive and said host processor through said storage control unit with a copy thereof being entered into said cache store; said addressing information including the address of a disk drive, a relative word address defining the location on a disk of the first word to be transferred, and the number of words to be transferred, and, said first means including means for converting said disk drive address, said relative word address and said word transfer length into addressing signals for addressing said cache store, whereby said host processors share said segment descriptor table and said cache store.

Claim 12

In a data processing system wherein a plurality of host processors issue commands including function and data addressing information to a storage control unit for reading data from or transferring data to at least one disk drive device attached to the storage control unit, the improvement comprising: a cache store for storing segments of data; means storing a segment descriptor table, said segment descriptor table having an entry corresponding to each segment of data residing in said cache store; control means including first means responsive to a command from a host processor calling for a read or a write from or to a disk for accessing said segment descriptor table to produce a hit signal if the segment or segments containing the data specified by said addressing information resides in said cache store, or a miss signal if it does not; means responsive to said hit signal for transferring the addressed data between said cache store and said host processor through said storage control unit; means responsive to said miss signal and said addressing information for transferring said addressed data between said disk drive and said host processor through said storage control unit with a copy thereof being entered into said cache store; said addressing information including the address of a disk drive, a relative word address defining the location on a disk of the first word to be transferred, and the number of words to be transferred, and, said first means including means for converting said disk drive address, said relative word address and said word transfer length into addressing signals for addressing said cache store, whereby said host processors share said segment descriptor table and said cache store.

Claim 13

The system as claimed in claim 9 including plural storage control units connected to plural disk drives and said host processors whereby said host processors and disk drives share said segment descriptor table and said cache store.

Claim 14

The system as claimed in claim 8 wherein said control means includes second means responsive to a store through command from a host processor for controlling the transfer of data from said host processor to said disk drive while simultaneously entering it into said cache store.

Claim 15

The system as claimed in claim 8 wherein a segment comprises a fixed number of words and said control means comprises means for accessing more than one segment in response to the addressing information in a single command.

Claim 16

The improvement as claimed in claim 8 and further comprising: means for storing a pointer table which makes the segment descriptor table fully associative; said first means including combining means for combining the disk drive address and said relative word address to obtain a pointer table address, means for accessing said pointer table address to obtain the address of an entry in said segment descriptor table, and, means responsive to said combining means for accessing said segment descriptor table with the address obtained from said pointer table.

Claim 17

The improvement as claimed in claim 8 wherein an entry in said segment descriptor table includes a hash link relative address field, a forward age link relative address field and a backward age link relative address field for linking together the segment descriptor table entries having duplicate hashed pointers.

Claim 18

The improvement as claimed in claim 14 wherein each segment descriptor table entry includes a device number and a segment device relative address, which designate the disk drive and the segment offset of the data from the first segment on the disk, for the data in the cache store segment corresponding to the segment descriptor table entry; and, said first means includes means for comparing the device number and segment device relative address from each entry in a segment descriptor table hash link with the addressing information from the host processor to produce said hit signal if a match is found or said miss signal if no match is found.