Transient and intermittent fault insertion

Claim 2

In an integrated circuit having a plurality of logic arranged for internal logic states to be held in serially accessed registers which are observable and controllable, fault insertion circuitry resident in said integrated circuit comprising: means for generating a plurality of fault classes having a first input for receiving scan path data words and a first output coupled to an input of said serially accessed registers, said fault classes comprising a permanent fault, a transient fault and intermittent faults; means for storing a fault word of said data words having a serial input, a serial output and a parallel output, said serial input being coupled to a second output of said fault classes generating means and said serial output being coupled to a second input of said fault classes generating means; and fault type generating means, coupled between said parallel output of said fault word storing means and said plurality of logic, for generating a fault type specified by said fault word for a time duration in accordance with a third output of said fault classes generating means.

Claim 3

The fault insertion circuitry as recited in claim 1 wherein: said fault classes generating means comprises means for generating a transient fault for a predetermined time duration.

Claim 4

The fault insertion circuitry as recited in claim 1 wherein: said fault classes generating means comprises means for generating a plurality of said intermittent faults, having a random time interval between each of said intermittent faults.

Claim 5

The fault insertion circuitry as recited in claim 1 wherein: said fault type generating means comprises decoding means for selecting said fault type specified by said fault word.

Claim 6

The fault insertion circuitry as recited in claim 4 wherein: said fault type generating means further comprises means coupled to said decoding means for interfacing said fault type to said plurality of logic in said integrated circuit.

Claim 7

The fault insertion circuitry as recited in claim 1 wherein: said fault type generating means comprises means at a logic one level.

Claim 8

The fault insertion circuitry as recited in claim 1 wherein: said fault type generating means comprises means for providing to said plurality of logic a fault signal stuck at a logic zero level.

Claim 9

The fault insertion circuitry as recited in claim 1 wherein: said fault type generating means comprises means for providing to said plurality of logic a fault signal having characteristics of an open circuit.

Claim 10

The fault insertion circuitry as recited in claim 1 wherein: said fault type generating means comprises means for providing to said plurality of logic a wired-AND bridging fault signal.

Claim 11

The fault insertion circuitry as recited in claim 1 wherein: said fault type generating means comprises means for providing to said plurality of logic a wired-OR bridging fault signal.

Claim 12

The fault insertion circuitry as recited in claim 1 wheren: said fault insertion circuitry comprises timing and control means for generating a plurality of control and timing signals used to shift said scan path data words to destination registers in said integrated circuit.

Claim 13

A fault insertion test system for verifying fault detection in a functional logic portion of an integrated circuit comprising: controller means for inserting a fault under program control into said integrated circuit with control and initialization data words and for monitoring the effect of said fault on said functional logic; means in said integrated circuit coupled to said controller means for generating a plurality of fault classes having a first input for receiving said control and initialization data words and a first output coupled to a serially accessed input of said functional logic, said fault classes comprising a permanent fault, a transient fault and intermittent faults; means for storing a fault word of said data words having a serial input, a serial output and a parallel output, said serial output being coupled to a second output of said fault classes generating means and said serial output being coupled to a second input of said fault classes generating means; and fault type generating means, coupled between said parallel output of said fault word storing means and said functional logic, for generating a fault type specified by said fault word for a time duration in accordance with a third output of said fault classes generating means.

Claim 14

A fault insertion test system for verifying fault detection in a functional logic portion of an integrated circuit comprising: controller means for inserting a fault under program control into said integrated circuit with control and initialization data words and for monitoring the effect of said fault on said functional logic; means in said integrated circuit coupled to said controller means for generating a plurality of fault classes having a first input for receiving said control and initialization data words and a first output coupled to a serially accessed input of said functional logic, said fault classes comprising a permanent fault, a transient fault and intermittent faults; means for storing a fault word of said data words having a serial input, a serial output and a parallel output, said serial output being coupled to a second output of said fault classes generating means and said serial output being coupled to a second input of said fault classes generating means; and fault type generating means, coupled between said parallel output of said fault word storing means and said functional logic, for generating a fault type specified by said fault word for a time duration in accordance with a third output of said fault classes generating means.

Claim 15

The fault insertion test system as recited in claim 12 wherein: said controller means comprises means for performing fault insertion testing wherein said effect of said fault insertion is detected by monitoring scan out serial data from said functional logic.

Claim 16

The fault insertion test system as recited in claim 12 wherein: said controller means comprises means for performing fault insertion testing wherein said effect of said fault insertion is detected by monitoring status data from said functional logic with diagnostic programs operating in said controller means.

Claim 17

The fault insertion test system as recited in claim 12 wherein: said integrated circuit comprises timing and control means coupled to said controller means for generating a plurality of control and timing signals used to shift said control and initialization data words to destination registers in said integrated circuit.

Claim 18

The fault insertion test system as recited in claim 12 wherein: said fault classes generating means comprises means for generating a transient fault for a predetermined time duration.

Claim 19

The fault insertion test system as recited in claim 12 wherein: said fault classes generating means comprises means for generating a plurality of said intermittent faults, having a random time interval between each of said intermittent faults.

Claim 20

The fault insertion test system as recited in claim 12 wherein: said fault type generating means comprises decoding means for selecting said fault type specified by said fault word.

Claim 21

The fault insertion test system as recited in claim 18 wherein: said fault type generating means further comprises means coupled to said decoding means for interfacing said fault type to said plurality of logic in said integrated circuit.

Claim 22

The fault insertion test system as recited in claim 12 wherein: said fault type generating means comprises means for providing to said plurality of logic a fault signal stuck at a logic one level.

Claim 23

The fault insertion test system as recited in claim 12 wherein: said fault type generating means comprises means for providing to said plurality of logic a fault signal stuck at a logic zero level.

Claim 24

The fault insertion test system as recited in claim 12 wherein: said fault type generating means comprises means for providing to said plurality of logic a fault signal having characteristics of an open circuit.

Claim 25

The fault insertion test system as recited in claim 12 wherein: said fault type generating means comprises means for providing to said plurality of logic a wired-AND bridging fault signal.

Claim 26

The fault insertion test system as recited in claim 12 wherein: said fault type generating means comprises means for providing to said plurality of logic a wired-OR bridging fault signal.

Claim 29

The method of fault insertion as recited in claim 25 wherein: said step of generating a plurality of fault classes comprises the step of generating a transient fault for a predetermined time duration.

Claim 30

The method of fault insertion as recited in claim 25 wherein: said step of generating a plurality of fault classes comprises the step of generating a plurality of said intermittent faults, having a random time interval between each of said intermittent faults.

Claim 31

The method of insertion as recited in claim 25 wherein: said step of generating a fault type comprises the step of decoding said fault word to generate a fault type signal.

Claim 32

The method of fault insertion as recited in claim 28 wherein: said step of generating a fault type further comprises the step of coupling said fault type signal to a circuit for interfacing said fault type to said plurality of logic in said integrated circuit.

Claim 33

The method of fault insertion as recited in claim 25 wherein: said step of generating a fault type comprises the step of providing to said plurality of logic a fault signal stuck at a logic one level.

Claim 34

The method of fault insertion as recited in claim 25 wherein: said step of generating a fault type comprises the step of providing to said plurality of logic a fault signal stuck at a logic zero level.

Claim 35

The method of fault insertion as recited in claim 25 wherein: said step of generating a fault type comprises the step of providing to said plurality of logic a fault signal having characteristics of an open circuit.

Claim 36

The method of fault insertion as recited in claim 25 wherein: said step of generating a fault type comprises the step of providing to said plurality of logic a wired-AND bridging fault signal.

Claim 37

The method of fault insertion as recited in claim 25 wherein: said step of generating a fault type comprises the step of providing to said plurality of logic a wired-OR bridging fault signal.

Claim 40

The method of verifying fault detection as recited in claim 35 wherein: said step of generating one of a plurality of fault classes comprises the step of generating a transient fault for a predetermined time duration.

Claim 41

The method of verifying fault detection as recited in claim 35 wherein: said step of generating one of a plurality of fault classes comprises the step of generating a plurality of said intermittent faults, having a random time interval between each of said intermittent faults.

Claim 42

The method of verifying fault detection as recited in claim 35 wherein: said step of generating a fault type comprises the step of decoding said fault word to generate a fault type signal.

Claim 43

The method of verifying fault detection as recited in claim 38 wherein: said step of generating a fault type further comprises the step of coupling said fault type signal to a circuit for interfacing said fault type to said functional logic in said integrated circuit.

Claim 44

The method of verifying fault detection as recited in claim 35 wherein: said step of generating a fault type comprises the step of providing to said functional logic a fault signal stuck at a logic one level.

Claim 45

The method of verifying fault detection as recited in claim 35 wherein: said step of generating a fault type comprises the step of providing to said functional logic a fault signal stuck at a logic zero level.

Claim 46

The method of verifying fault detection as recited in claim 35 wherein: said step of generating a fault type comprises the step of providing to said functional logic a fault signal having characteristics of an open circuit.

Claim 47

The method of verifying fault detection as recited in claim 35 wherein: said step of generating a fault type comprises the step of providing to said functional logic a wired-AND bridging fault signal.

Claim 48

The method of verifying fault detection as recited in claim 35 wherein: said step of generating a fault type comprises the step of providing to said functional logic a wired-OR bridging fault signal.

Claim 49

The method of verifying fault detection as recited in claim 35 wherein: said step of monitoring said effect of said fault insertion with said controller means comprises the step of analyzing scan out serial data from said functional logic.

Claim 50

The method of verifying fault detection as recited in claim 35 wherein: said step of monitoring said effect of said fault insertion with said controller means comprises the step of monitoring status data from said functional logic with diagnostic programs operating in said controller means.